sl28eb719 Silicon Laboratories, sl28eb719 Datasheet - Page 22

• Manufacturer Part Number: sl28eb719
• Description: Eproclock Generator For Intel Tunnel Creek & Top Cliff
• Manufacturer: Silicon Laboratories

Document History Page
Document Title: SL28EB719 PC EProClock
DOC#: SP-AP-0005 (Rev. AB)
DOC#: SP-AP-0005 (Rev. AB)
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
REV.
AA
AB
ECR#
1458
1640
03/17/10
06/23/10
Issue
Date
Change
Orig. of
JMA
JMA
Initial Release
1. Added CLKIN feature
2. Added Period Spec for CPU, SRC, and DOT96
3. Added Cycle-to-cycle jitter spec for CPU2/SRC5 (ITP clock)
4. Removed REF wording from 14.318MHz
5. Reduced IDD to 130mA from 200mA
6. Reduced PCI clocks cycle-to-cycle jitter to 300ps from 500ps
7. Reduced 25MHzclock cycle-to-cycle jitter to 300ps from 500ps
8. Reduced 48/12MHz clocks cycle-to-cycle jitter to 300ps from 350ps
9. Reduced 14.318MHz clock cycle-to-cycle jitter to 500ps from 1000ps
10. Reduced SATA75 clock cycle-to-cycle jitter to 125ps from 250ps
11. Removed skew for 14MHz
12. Updated CPU2 Cycle-to-cycle jitter to be 125ps from 85ps
13. Updated Package information
14. Added PD# label to pin configuration on page 1
15. Updated MIL-STD to JEDEC
16. Removed Prliminary wording
17. Added period spec for 83.33, 133, and 166MHz
18. Updated block diagram
®
Generator for Intel Tunnel Creek & Top Cliff
Description of Change
SL28EB719
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