sl28eb719 Silicon Laboratories, sl28eb719 Datasheet - Page 14

• Manufacturer Part Number: sl28eb719
• Description: Eproclock Generator For Intel Tunnel Creek & Top Cliff
• Manufacturer: Silicon Laboratories

DOC#: SP-AP-0005 (Rev. AB)
PCI/SRC_STP# Deassertion
The deassertion of the PCI/SRC_STP# signal causes all PCI
and stoppable PCIF to resume running in a synchronous
manner within two PCI clock periods, after PCI/SRC_STP#
transitions to a HIGH level. Simlarly, PCI/SRC_STP#
deassertion will cause stoppable SRC clocks to resume
running. For SRC clocks deassertion description, please refer
to CPU_STP# description.
.
.
SR C 100 M H z
CK505 Core Logic
CKPWRGD/PD#
All Other Clocks
CK505 SMBUS
P C I_S T P #
REF Oscillator
PLL2 & PLL3
CK505 State
CPU_STP#
BSEL[0..2]
PCI_STP#
CPU1
PLL1
Vcc
P C I_F
P C I
Off
Off
Figure 9. PCI_STP# Deassertion Waveform
T su
2.0V
T_delay t
T drive_ S R C
3.3V
Figure 10. BSEL Serial Latching
C l o c k O f f t o M 1
Off
Latches Open
FSC
.
FSB
T_delay3
FSA
T_delay2
M1
SL28EB719
Locked
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