sl28eb719 Silicon Laboratories, sl28eb719 Datasheet
sl28eb719
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sl28eb719 Summary of contents
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... SEL12_48* 10 DOT96 48M / FSA** 12 48M 12 / 48M GND_SATA 17 14.318M SATA75M / SRC0 18 SATA75M# / SRC0# 19 VDD_SATA Internal 100K-ohm pull-up resistor ** Internal 100K-ohm pull down resistor 1+(512) 416-8500 1+(512) 416-9669 SL28EB719 ® Programmable Technology SATA75 DOT96 48M 48M/12M 33M 25M x0/ x1/2 x1 ...
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... Power supply for SATA clock Ground for SRC clocks 3.3V Power supply for SRC clocks ITP_EN = 0 @ CK_PWRGD assertion = SRC6 ITP_EN = 1 @ CK_PWRGD assertion = CPU2 ITP_EN = 0 @ CK_PWRGD assertion = SRC6 ITP_EN = 1 @ CK_PWRGD assertion = CPU2 3.3V Power supply for CPU clocks Ground for clocks SL28EB719 Description Page ...
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... Differential skew control on true or compliment or both - Differential duty cycle control on true or compliment or both - Differential amplitude control - Differential and single-ended slew rate control - Program Internal or External series resistor on single-ended clocks - Program different spread profiles - Program different spread modulation rate SL28EB719 Description Page ...
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... The offset of the indexed byte is encoded in the command code described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description SL28EB719 SATA PCI 100.00 33.33 100.00 33 ...
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... Write 10 Acknowledge from slave 18:11 Command Code–8 bits 19 Acknowledge from slave 27:20 Data byte–8 bits 28 Acknowledge from slave 29 Stop DOC#: SP-AP-0005 (Rev. AB) SL28EB719 Block Read Protocol Bit Description 1 Start 8:2 Slave address–7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code–8 bits ...
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... Output enable for 14M 0 = Output Disabled Output Enabled Output enable for 25M 0 = Output Disabled Output Enabled Output enable for 12_48M 0 = Output Disabled Output Enabled Output enable for PCI0 0 = Output Disabled Output Enabled Output enable for PCIF 0 = Output Disabled Output Enabled RESERVED SL28EB719 ) Page ...
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... CPU0 Free Run Control 0= Free Running, 1= Stoppable RESERVED Description RESERVED RESERVED RESERVED SATA75/SRC0 Free Run Control 0= Free Running, 1= Stoppable SRC6 Free Run Control 0= Free Running, 1= Stoppable SRC2 Free Run Control 0= Free Running, 1= Stoppable SRC1 Free Run Control 0= Free Running, 1= Stoppable RESERVED SL28EB719 Page ...
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... In order to read beyond Byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read. Description RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED PCI0 Free Run Control 0= Free Running, 1= Stoppable PCIF Free Run Control 0= Free Running, 1= Stoppable SL28EB719 Page ...
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... RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Description Drive Strength Control - Bit[2:0] Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’ Description Drive Strength Control - Bit[2:0] Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’ SL28EB719 Page ...
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... Driven Low Running Running Running Clock driven high Clock driven low Clock# driven low Clock# driven low Running Running All Differential Clocks w/ Strap Clock Clock# Hi-z Low Low SL28EB719 Description Description CLKREQ# Asserted SMBus OE Disabled Driven low Clock driven low Page ...
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... The SL28EB719 requires a Parallel Resonance Crystal. Substituting a series resonance SL28EB719 to operate at the wrong frequency and violates the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm perfor- mance ...
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... < > 0.2-0 ait for S am ple S els D elay V TT_PW tate 1 State Figure 5. CKPWRGD Timing Diagram SL28EB719 D evice is not affected, V TT_P ignored State Page ...
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... No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. Figure 6. CPU_STP# Assertion Waveform Tdrive_CPU_STP#,10 ns>200 mV Figure 7. CPU_STP# Deassertion Waveform . ). Figure 8. PCI_STP# Assertion Waveform SL28EB719 Page ...
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... CK505 Core Logic PLL1 CPU1 PLL2 & PLL3 All Other Clocks REF Oscillator DOC#: SP-AP-0005 (Rev. AB drive_ 3.3V 2.0V T_delay t FSC FSB Off Latches Open T_delay3 Figure 10. BSEL Serial Latching SL28EB719 FSA M1 Locked T_delay2 Page ...
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... Except internal pull-down resistors, 0 < Except internal pull-up resistors, 0 < – All outputs enabled. SE clocks with 8” traces. Differential clocks with 7” traces. Loading per CK505 spec. SL28EB719 Min. Max. Unit – 4.6 V –0.5 4 –65 150 ° ...
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... Measured at 0V differential at 0.1s Measured at 0V differential at 0.1s Measured at 0V differential at 1 clock Measured at 0V differential at 1 clock Measured at 0V differential Measured at 0V differential Measured at 0V differential Measured at 0V differential Measured differentially from ±150 mV Measured single-endedly from ±75 mV SL28EB719 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – ...
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... Measured differentially from ±150 mV Measured single-endedly from ±75 mV Measured at 0V differential Measured at 0V differential at 1 clock Measured at 0V differential at 1 clock Measured differentially from ±150 mV Measured single-endedly from ±75 mV Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V SL28EB719 Min. Max. Unit 300 550 9.99900 10.0010 ns 10 ...
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... Measurement at 0.8V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V SL28EB719 Min. Max. Unit 12.27365 16.27665 ns 11.87365 16.07665 ns 1.0 4.0 V/ns – 250 ps – 300 ps – ...
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... Figure 11. Single-ended clocks Single Load Configuration Figure 12. Single-ended Output Signals (for AC Parameters Measurement) For Differential Clock Signals This diagram shows the test load configuration for the differential clock signals DOC#: SP-AP-0005 (Rev. AB) Figure 13. 0.7V Differential Load Configuration SL28EB719 Page ...
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... Figure 14. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) Figure 15. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0005 (Rev. AB) SL28EB719 Page ...
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... Ordering Information Part Number Lead-free SL28EB719ALI 48-pin TSSOP SL28EB719ALIT 48-pin TSSOP– Tape and Reel Package Diagrams DOC#: SP-AP-0005 (Rev. AB) Package Type 48-Lead TSSOP SL28EB719 Product Flow Industrial, -40 to 85C Industrial, -40 to 85C Page ...
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... Document History Page Document Title: SL28EB719 PC EProClock DOC#: SP-AP-0005 (Rev. AB) Issue Orig. of REV. ECR# Date Change AA 1458 03/17/10 JMA AB 1640 06/23/10 JMA The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil- icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein ...