sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 33

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

3.5.1
Stop2 mode provides very low standby power consumption and maintains the contents of RAM and the
current state of all of the I/O pins. To enter stop2, the user must execute a STOP instruction with stop2
selected (PPDC = 1) and stop mode enabled (STOPE = 1). In addition, the LVD must not be enabled to
operate in stop (LVDSE = LVDE = 1). If the LVD is enabled in stop, then the MCU enters stop3 upon the
execution of the STOP instruction regardless of the state of PPDC.
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit
of stop2, these values can be restored by user software before pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned
off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ADC. Upon entry
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a logic 1 is written to PPDACK in SPMSC2.
Exit from stop2 is done by asserting either of the wake-up pins: RESET or IRQ/TPMCLK, or by an RTI
interrupt. IRQ/TPMCLK is always an active low input when the MCU is in stop2, regardless of how it was
configured before entering stop2.
Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is
written to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch
to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
Freescale Semiconductor
1
2
Mode
Stop2
Stop3
PPDC is the partial power down control bit, see
Register
Crystal oscillator can be configured to run in stop3. See the ICG registers.
Stop2 Mode
(SPMSC2),’’ for details.
PPDC
1
0
1
CPU, Digital
Peripherals,
Standby
Flash
Off
SC9S08MZ16 MCU Data Sheet, Rev. 0 Draft C
Standby
Standby
RAM
Table 3-1. Stop Mode Behavior
Section 5.9.9, “System Power Management Status and Control 2
ICG
Off
Off
2
Optionally on
Disabled
ADC
Regulator
Standby
Standby
States held Optionally on
States held Optionally on
I/O Pins
Chapter 3 Modes of Operation
RTI
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