sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 133

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sc9s08mz16

Manufacturer Part Number
sc9s08mz16
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
If this mode is entered due to a reset, f
mode is entered from FLL engaged internal, f
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock), f
If this mode is entered from off mode, f
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
8.5.3
FLL engaged internal (FEI) is entered when any of the following conditions occur:
Freescale Semiconductor
CLKS bits are written to 01
The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
ICGDCLK
DCOS
COUNTER ENABLE
FLL Engaged, Internal Clock (FEI) Mode
CLKST
SUBTRACTOR
REFERENCE
DIVIDER (/7)
RANGE
will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked.
LOCK
MFD
RANGE
OVERFLOW
Figure 8-12. Detailed Frequency-Locked Loop Block Diagram
LOSS OF CLOCK
LOLS
DETECTOR
LOCK AND
LOC
ICGIRCLK
ERCS
SC9S08MZ16 MCU Data Sheet, Rev. 1
DIGITAL
CLKST
FILTER
LOOP
ICGDCLK
FLT
ICGDCLK
LOC
COUNTER
ICGDCLK
PULSE
will default to f
will be equal to the frequency of ICGDCLK before
ICGIF
CONTROLLED
OSCILLATOR
will maintain the previous frequency.If this mode
FLL ANALOG
DIGITALLY
RESET AND
INTERRUPT
SELECT
CIRCUIT
CLOCK
CONTROL
CLKS
LOLR
ICGDCLK
Self_reset
ICG2DCLK
1x
2x
LOCRE
which is nominally 8 MHz. If this
FREQUENCY
DIVIDER (R)
REDUCED
RFD
Internal Clock Generator (S08ICGV4)
FREQUENCY-
LOOP (FLL)
LOCKED
ICGOUT
RESET
IRQ
133

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