si5338b Silicon Laboratories, si5338b Datasheet - Page 25

• Manufacturer Part Number: si5338b
• Description: I2c-programmable Any-rate , Any-output Quad Clock Generator
• Manufacturer: Silicon Laboratories

Pin #
10
11
12
13
14
15
16
17
6
7
8
9
Pin Name
VDDO3
VDDO2
VDDO1
CLK3B
CLK3A
CLK2B
CLK2A
CLK1B
INTR
VDD
SCL
IN6
Table 19. Si5338 Pin Descriptions (Continued)
VDD
VDD
VDD
VDD
I/O
O
O
O
O
O
O
I
I
Signal Type
Open Drain
LVCMOS
Supply
Supply
Supply
Supply
Multi
Multi
Multi
Multi
Multi
Multi
Rev. 0.3
GND
In clock generator mode, this pin functions as a GND
pin. It must be tied low.
FDBKB
In zero delay buffer mode, one side of a differential input
should be supplied to this pin. The other side of the
differential input should be supplied to IN5. This pin
functions as the feedback clock input for the PLL phase
frequency detector.
Core Supply Voltage
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 µF bypass capacitor should be located very close to
this pin.
Interrupt
This pin functions as a maskable interrupt output.
0 = No interrupt.
1 = Interrupt present.
This pin requires an external 1 kpull-up resistor.
Output Clock B for Channel 3
May be a single-ended output or half of a differential out-
put with CLK3A being the other differential half.
Output Clock A for Channel 3
May be a single-ended output or half of a differential
output with CLK3B being the other differential half.
Output Clock Supply Voltage
Supply voltage for CLK3A,B. If CLK3 is not used, this pin
must be tied to pin 7 and/or pin 24.
I
Output Clock B for Channel 2
May be a single-ended output or half of a differential
output with CLK2A being the other differential half.
Output Clock A for Channel 2
May be a single-ended output or half of a differential
output with CLK2B being the other differential half.
Output Clock Supply Voltage
Supply voltage for CLK2A,B. If CLK2 is not used, this pin
must be tied to pin 7 and/or pin 24.
Output Clock Supply Voltage
Supply voltage for CLK1A,B. If CLK1 is not used, this pin
must be tied to pin 7 and/or pin 24.
Output Clock B for Channel 1
May be a single-ended output or half of a differential
output with CLK1A being the other differential half.
If unused, this pin must be tied to VDD pin 24.
2
C Serial Clock Input
Description
Si5338
25