si5338b Silicon Laboratories, si5338b Datasheet - Page 15

• Manufacturer Part Number: si5338b
• Description: I2c-programmable Any-rate , Any-output Quad Clock Generator
• Manufacturer: Silicon Laboratories

input clock and output clocks must be the same in the
zero delay buffer mode of operation.
It is recommended to use CLK3 as the feedback source
to minimize the routing length.
For differential feedback, the CLK3A,B pins should be
routed to the N5,6 pins, respectively. For single-ended
feedback, CLK3A should be dc-connected to IN4.
The input at IN4 is internally AC coupled and will
tolerate 3.63 V regardless of the VDD supply voltage.
The signal applied at IN4 should be dc-coupled. An
input applied to IN5 and IN6 must be ac coupled and a
100  resister should be placed between IN5 and IN6
and located very close to the device pins.
Unused input clocks must be connected to ground.
Consult “AN408: Si5338 I/O Termination Guidelines” for
clock input and clock output termination guidelines for
the Si5338.
2.4. Clock Multiplication Settings
Using Silicon Laboratories' patent-pending MultiSynth
technology, the Si5338 can generate up to four unique
non-integer related output frequencies on up to eight
clock outputs with zero ppm frequency error. Each
output is independently user-programmable to any
frequency up to 350 MHz and select frequencies to
700 MHz. Note that if one or more output clocks are
configured to be >350 MHz, then the maximum
frequency of the remaining output clocks may be limited
to the range of 275–350 MHz. Consult the Si5338
configuration software for more details.
Independent, non-integer related output frequencies are
easily configured by selecting a unique MultiSynth
output divider value M for each output clock. The
MultiSynth output and feedback dividers are fractional
dividers expressed in terms of an integer and a fraction.
The resolution of the fractional part is the ~1e
means that, for all intents and purposes, the output
frequency can be defined exactly from the input
frequency. The input to output frequency transfer
equation is as follows:
–9
, which
Rev. 0.3
Full integer values in the MultiSynth dividers always
provide the best jitter performance and lower power.
Following a manual change in any divider value, the
device must be reset using the SOFT_RESET register
to make the change effective. When the Rn divider is
not set to 1, the output phase for that channel may
initiate to an incorrect value. Additionally, since the
frequency
referenced to the output of the MultiSynth, non-unity Rm
divider settings will affect the expected frequency
change from an increment and decrement. The phase
increment and decrement function is unaffected by the
Rn divider setting.
There may be multiple valid combinations of divider
values for a particular frequency plan. To simplify device
configuration, Silicon Labs provides Si5338 software
that determines the valid combinations and selects the
optimum
performance and power consumption. The Si5338
software can be downloaded from www.silabs.com/
timing.
f
where:
f
f
Pn
Rn = Output divider R0, R1, R2, or R3
N = MultiSynth feedback divider
M = MultiSynth output divider
OUT
OUT
IN
=
=
=
Input frequency
=
Input divider P1 or P2
Values of 1, 2, 4, 8, 16, and 32 are supported
Values of 1, 2, 4, 8, 16, and 32 are supported
Output frequency
-------------------------------- -
Pn M Rn
PLL
increment
f

IN


N
divider
and
settings
decrement
based
Si5338
function
on
jitter
15
is