si5338b Silicon Laboratories, si5338b Datasheet - Page 20

• Manufacturer Part Number: si5338b
• Description: I2c-programmable Any-rate , Any-output Quad Clock Generator
• Manufacturer: Silicon Laboratories

Si5338
2.14. Device Interrupt and Alarms
The Si5338 has a maskable interrupt output pin INTR
that can be used to monitor the status of the device.
Status conditions for system calibration in process,
NVM download error, NVM store error, PLL loss of lock
(LOL), input clock loss of signal (LOS), and feedback
clock LOS can be individually masked to the INTR
output pin as shown in Table 18. Each of these status or
alarm conditions can also be individually monitored via
the read-only registers accessible via the I
The loss of lock algorithm works by continuously
monitoring the frequency difference between the input
clock frequency and the feedback clock frequency
supplied to the device phase frequency detector. When
this frequency difference is greater than 1000 ppm, a
loss of lock condition is declared. However one must
also take into account that the PLL will track a frequency
shift/drift of the input clock for up to ~10000 ppm. Hence
the input clock frequency may need to be ~11000 ppm
in error or more before a LOL condition is declared. The
LOS function will assert when the reference clock input
signal is removed. When either LOL or LOS occurs, the
clock outputs are squelched. When squelched, the
output clocks can be programmed to be either a high or
a low.
20
System Calibration in Process
CLKIN± Loss of Signal
FDBK± Loss of Signal
NVM Download Error
PLL Loss of Lock
NVM Store Error
Status/Alarm
Table 18. Si5338 Status and Alarm Controls
(Read Only, Self-Clearing)
NVM_STORE_ERR
NVM_DLD_ERR
Status Register
LOS_CLKIN
LOS_FDBK
SYS_CAL
2
SYS_LOL
C interface.
Rev. 0.3
The device always indicates the PLL lock status on the
SYS_LOL read-only register bit. The device always
indicates the PLL lock status on the INTR pin if the
interrupt mask for that bit is not set. To mask an LOL
event from appearing on the INTR output pin, set
SYS_LOL_MASK to 1. The SYS_LOL register bit is
self-clearing once the PLL reasserts lock. A sticky bit is
also available for an LOL event (SYS_LOL_STK).The
Si5338 monitors the input clock and feedback path for
LOS. The LOS algorithm monitors input clock edges
and declares an LOS when signal edges are not
detected over a 5 µsec observation period. Once a loss
of signal event is detected, the device output clocks are
squelched. Optional settings to stop the output clock(s)
high or low are also available. The device always
indicates the loss of signal status on the LOS_CLKIN
and LOS_FDBK read-only register bits. The device
always indicates the loss of signal status on the INTR
pin if the interrupt mask is not set. To mask an LOS
event from appearing on the INTR output pin, set
LOS_CLKIN_MASK and LOS_FDBK_MASK to 1. The
LOS_CLKIN and LOS_FDBK register bits are self-
clearing once the clock signal returns and is revalidated.
Sticky bits are also available for an LOS alarm
(LOS_CLKIN_STK and LOS_FDBK_STK). A loss of
signal event will always cause the loss of lock alarm to
trigger.
Sticky Bit Register
NVMSTORE_STK
LOS_CLKIN_STK
LOS_FDBK_STK
SYS_CAL_STK
SYS_LOL_STK
NVMERR_STK
LOS_CLKIN_MASK
LOS_FDBK_MASK
SYS_CAL_MASK
SYS_LOL_MASK
NVMERR_MASK
NVMERR_MASK
Mask Register