si5338b Silicon Laboratories, si5338b Datasheet - Page 17

• Manufacturer Part Number: si5338b
• Description: I2c-programmable Any-rate , Any-output Quad Clock Generator
• Manufacturer: Silicon Laboratories

software. All unused clock output channels must have
their respective VDD0x supply voltage connected to pin
7 and 24 VDD. See Table 12 for the available options.
If an output driver is not used the entire channel may be
powered down to save the most current. Alternately
each output driver may be disabled individually or all
drivers may be disabled simultaneously. When an
output driver is disabled there is a choice to have the
output be a high, low or high Z. For a better
understanding of the output driver capabilities of the
Si5338 please read AN408. Complete control of the
output drivers is simplified by using the Si5338
Programmer software.
2.7. Output Clock Initial Phase Offset
The Si5338 supports programmable phase adjustment
between output clocks with an accuracy of at least
20 ps. This feature can be used to compensate for trace
length mismatches between different output clocks.
Phase offset is independently programmable for every
output clock. The phase adjustment range is ±45 ns.
The initial phase of each clock output is also
configurable with an accuracy of 20 ps. The Si5338
configuration software should be used to calculate the
correct phase offset value in conjunction with the VCO
clock rate for a given frequency plan. Once the device
output clock initial phase offset is programmed, a
subsequent soft reset will not change this phase offset.
When the Rn divider is not set to 1, the initial phase
offset function is not supported.
Voltage
Supply
VDD0x
1.5
1.8
2.5
3.3
CMOS
X
X
X
Table 12. Output Driver Signal Format Selection
SSTL
X
X
X
HSTL
X
Rev. 0.3
2.8. Output Clock Phase
The Si5338 has a digitally-controlled phase increment/
decrement feature that allows the user to adjust the
phase of each output clock in relation to the other output
clocks. The phase of each output clock can be adjusted
with an accuracy of < 20 ps over a range of ±45 ns. The
maximum clock output frequency supported in this
mode of operation is f
frequency of the device's internal Voltage Controlled
Oscillator for the configured frequency plan. The phase
transition is glitchless. The Si5338 programmer must be
used to set the magnitude of the phase step and
calculate the register values for the phase increment/
decrement feature. This feature is also available via pin
control for the Si5338D/Si5338E/Si5338F and will allow
the phase to increment or decrement up to a rate of
1 MHz.
When pin control is desired, pins 1 and 2 must be used
for the input clock (crystal) so that the IN3 and IN4 pins
are available for increment/decrement. Pin control of
phase requires a positive pulse that is greater than
100 ns followed by at least 100 ns of low level. Pin
control of phase increment or decrement can apply to
one or more of the outputs. Each clock output can be
programmed to change phase with different step sizes.
The NVM can be programmed at the factory to set the
magnitude of the phase increment and to which outputs
it is applicable. Using pin control, the latency (phase)
can be incremented as fast as 100 kHz. The magnitude
of the change must be set using the Si5338
programmer.
I
possible on all Si5338 devices and necessary on the
Si5338A,B,C,G,H,J as these devices do not provide pin-
controlled phase adjustment. Using the I2C interface
will allow the phase of each output clock to be
independently controlled.Table 13 lists the registers that
control activation of phase increment and decrement.
2
LVPECL
C control of phase increment and decrement is also
X
X
Increment/Decrement
LVPECL low
power
X
X
VCO
/8, where f
LVDS
X
X
X
Si5338
VCO
HCSL
X
X
X
is the
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