si5351 Silicon Laboratories, si5351 Datasheet - Page 9

• Manufacturer Part Number: si5351
• Description: Si5350a Factory-programmable Cmos Clock Generator
• Manufacturer: Silicon Laboratories

2.1.2. External Clock Input (CLKIN)
The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to
30 MHz.
2.1.3. Voltage Control Input (VC)
The internal VCXO generates a center frequency in the range of 600 MHz to 800 MHz that is controlled (pulled) by
the voltage applied at the VC input pin. The unique design of the VCXO eliminates the need for an external pullable
crystal. Only a standard, low-cost, fixed-frequency (25 MHz or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable from 10ppm to 1000ppm to satisfy a wide variety of applications. Key
advantages of the VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90%
of VDD), and reliable startup and operation.
2.2. Synthesis Stages
The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
the lower frequency input references to a high-frequency intermediate clock in the range of 600 - 800 MHz. The
second stage uses high-resolution MultiSynth fractional dividers to generate frequencies in the range of ~391 kHz
to 100 MHz. It is also possible to generate two frequencies up to 133 MHz on two or more of the outputs.
A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous
clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread
spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
Since the VCXO already generates a high-frequency intermediate clock, it is fed directly into the second stage of
synthesis. The MultiSynth high-resolution dividers synthesize the VCXO center frequency to any frequency in the
range of ~391 kHz to 133 MHz. The center frequency is then controlled (or pulled) by the VC input. An interesting
feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This creates a
VCXO with multiple output frequencies controlled from one VC input as shown in Figure 3.
2.3. Output Stage
An additional level of division (R) is available at the output stage for generating clocks as low as 8 kHz. All output
drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage
signal level (3.3V or 2.5V) at each of the four 2-output banks.
Figure 3. Using the Si5351 as a Multi-Output VCXO
Voltage
Control
VC
XA
VCXO
OSC
XB
Crystal (non-pullable)
Fixed Frequency
Synth
Synth
Synth
Multi
Multi
Multi
0
1
2
Rev. 0.1
R0
R1
R2
CLK0
CLK1
CLK2
controlled by the VC input
generated from CLK0 is
Additional MultiSynths
The clock frequency
can be “linked” to the
VCXO to generate
additional clock
frequencies
Si5351A/B/C
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