si5351 Silicon Laboratories, si5351 Datasheet - Page 23

• Manufacturer Part Number: si5351
• Description: Si5350a Factory-programmable Cmos Clock Generator
• Manufacturer: Silicon Laboratories

Reset value = 0000 0000
Register 17. CLK1 Control
Bit
3:2
1:0
Name
Type
7
6
5
4
Bit
CLK1_SRC[1:0] Output Clock 0 Input Source.
CLK1_PDN
CLK1_PDN
MS0_SRC
CLK1_INV
MS0_INT
Reserved
Name
R/W
D7
MS1_INT
Clock 0 Power Down.
This bit allows powering down the CLK1 output driver to conserve power when the out-
put is unused.
0: CLK1 is powered up.
1: CLK1 is powered down.
MultiSynth 0 Integer Mode.
This bit can be used to force MS0 into Integer mode to improve jitter performance. Note
that the fractional mode is necessary when a delay offset is specified for CLK1.
0: MS0 operates in fractional division mode.
1: MS0 operates in integer mode.
MultiSynth Source Select for CLK1.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 0 Invert.
0: Output Clock 0 is not inverted.
1: Output Clock 0 is inverted.
These bits determine the input source for CLK1.
00: Select the XTAL as the clock source for CLK1. This option by-passes both synthesis
stages (PLL/VCXO & MultiSynth) and connects CLK1 directly to the oscillator which gen-
erates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK1. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK1 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK1. Select this option when using the Si5351
to generate free-running or synchronous clocks.
Reserved. Leave as default.
R/W
D6
MS1_SRC
R/W
D5
CLK1_INV
R/W
Rev. 0.1
D4
Function
R/W
CLK1_SRC[1:0]
D3
R/W
D2
Si5351A/B/C
R/W
D1
R/W
D0
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