si5351 Silicon Laboratories, si5351 Datasheet - Page 25

• Manufacturer Part Number: si5351
• Description: Si5350a Factory-programmable Cmos Clock Generator
• Manufacturer: Silicon Laboratories

Reset value = 0000 0000
Register 19. CLK3 Control
Name
3:2
1:0
Bit
Type
7
6
5
4
Bit
CLK3_SRC[1:0] Output Clock 0 Input Source.
CLK3_PDN
CLK3_PDN
MS0_SRC
CLK3_INV
Reserved
MS0_INT
Name
R/W
D7
MS3_INT
R/W
Clock 0 Power Down.
This bit allows powering down the CLK3 output driver to conserve power when the out-
put is unused.
0: CLK3 is powered up.
1: CLK3 is powered down.
MultiSynth 0 Integer Mode.
This bit can be used to force MS0 into Integer mode to improve jitter performance.
Note that the fractional mode is necessary when a delay offset is specified for CLK3.
0: MS0 operates in fractional division mode.
1: MS0 operates in integer mode.
MultiSynth Source Select for CLK3.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 0 Invert.
0: Output Clock 0 is not inverted.
1: Output Clock 0 is inverted.
These bits determine the input source for CLK3.
Reserved. Leave as default.
D6
MS3_SRC
R/W
D5
CLK3_INV
R/W
Rev. 0.1
D4
Function
R/W
CLK3_SRC[1:0]
D3
R/W
D2
Si5351A/B/C
R/W
D1
R/W
D0
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