si5351 Silicon Laboratories, si5351 Datasheet - Page 8

• Manufacturer Part Number: si5351
• Description: Si5350a Factory-programmable Cmos Clock Generator
• Manufacturer: Silicon Laboratories

Si5351A/B/C
2. Functional Description
The Si5351 is a versatile I
oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
Figure 1. The device consists of an input stage, two synthesis stages, and an output stage.
The input stage accepts an external crystal (XTAL), a clock input (CLKIN), or a control voltage input (VC)
depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
generating output frequencies as low as 8 kHz. Crosspoint switches at each of the synthesis stages allows total
flexibility in routing any of the inputs to any of the outputs.
Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
synthesize clocks for multiple clock domains in a design.
2.1. Input Stage
2.1.1. Crystal Inputs (XA, XB)
The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
Internal load capacitors (C
to the Si5351. Options for internal load capacitors are 6, 8, or 10 pF. Crystals with alternate load capacitance
requirements are supported using additional external load capacitors as shown in Figure 2. Refer to application
note AN551 for crystal recommendations.
8
25 or 27
XTAL
MHz
10-100
CLKIN
MHz
VC
XA
XB
Stage
Input
VCXO
OSC
Div
kv
Figure 2. External XTAL with Optional Load Capacitors
L
) are provided to eliminate the need for external components when connecting a crystal
2
C programmable clock generator that is ideally suited for replacing crystals, crystal
MHz
<30
Synthesis
Stage 1
Figure 1. Si5351 Block Diagram
(VCXO)
600-800
PLL A
PLL B
(SSC)
Additional external
MHz
load capacitors
Optional
C
C
L
L
600-800
MHz
XB
XA
C
Rev. 0.1
L
Synthesis
Stage 2
Synth
Synth
Synth
Synth
Synth
Synth
Synth
Synth
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
C
0
1
2
3
4
5
6
7
L
Selectable internal
6 pF, 8 pF, 10 pF
load capacitors
391 kHz –
133 MHz
R0
R1
R2
R3
R4
R5
R6
R7
Output
Stage
VDDOA
CLK0
CLK1
VDDOB
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
8 kHz – 133 MHz
8 kHz – 133 MHz
8 kHz – 133 MHz
8 kHz – 133 MHz
8 kHz – 133 MHz
8 kHz – 133 MHz
8 kHz – 133 MHz
8 kHz – 133 MHz
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