si5351 Silicon Laboratories, si5351 Datasheet - Page 16

• Manufacturer Part Number: si5351
• Description: Si5350a Factory-programmable Cmos Clock Generator
• Manufacturer: Silicon Laboratories

Si5351A/B/C
7. Register Map Summary
The following is a summary of the register map used to read status, control, and configure the Si5351.
16
Register
173–176
178–182
184–255
26–172
10–14
4–8
177
183
15
16
17
18
19
20
21
22
23
24
25
0
1
2
3
9
OEB_CLK7
CLK0_PDN
CLK1_PDN
CLK2_PDN
CLK3_PDN
CLK4_PDN
CLK5_PDN
CLK6_PDN
CLK7_PDN
PLLB_RST
SYSCAL_
SYSCAL_
SYS_INIT
CLK7_EN
MASK
STKY
CLK3_DIS_STATE
CLK7_DIS_STATE
7
0
XTAL_CL
OEB_CLK6
CLK6_EN
MS0_INT
MS1_INT
MS2_INT
MS3_INT
MS4_INT
MS5_INT
MS6_INT
MS7_INT
LOS_B_
LOS_B_
LOL_B
MASK
STKY
6
0
Use ClockBuilder Desktop Software to Determine These Register Values.
PLL, MultiSynth, and output clock delay offset Configuration Registers.
OEB_CLK5
PLLA_RST
MS0_SRC
MS1_SRC
MS2_SRC
MS3_SRC
MS4_SRC
MS5_SRC
MS6_SRC
MS6_SRC
CLK5_EN
LOL_A _
LOL_A_
LOL_A
MASK
STKY
CLK2_DIS_STATE
CLK6_DIS_STATE
5
0
OEB_CLK4
CLK0_INV
CLK1_INV
CLK2_INV
CLK3_INV
CLK4_INV
CLK5_INV
CLK6_INV
CLK7_INV
CLK4_EN
MASK
LOS_
STKY
LOS_
LOS
Rev. 0.1
4
0
Reservedt
Reserved
Reserved
Reserved
Reserved
OEB_CLK3
PLLB_SRC
CLK3_EN
CLK1_DIS_STATE
CLK5_DIS_STATE
3
OEB_CLK2
PLLA_SRC
CLK2_EN
2
OEB_CLK1
CLK1_EN
CLK0_DIS_STATE
CLK4_DIS_STATE
1
0
REVID[1:0]
OEB_CLK0
CLK0_EN
0
0