upd78f0134hgka1-9et-a Renesas Electronics Corporation., upd78f0134hgka1-9et-a Datasheet - Page 540

• Manufacturer Part Number: upd78f0134hgka1-9et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

540
Internal
Oscillator
Main
clock
High-
speed
system
clock
oscillator,
subsystem
clock
oscillator
Prescaler
CPU
clock
Function
OSTS:
Oscillation
stabilization
time select
register
Details of
Function
To set the STOP mode when the high-speed system clock is used as the CPU
clock, set OSTS before executing a STOP instruction.
Before setting OSTS, confirm with OSTC that the desired oscillation stabilization
time has elapsed.
If the STOP mode is entered and then released while the internal oscillation clock
is being used as the CPU clock, set the oscillation stabilization time as follows.
The oscillation stabilization time counter counts up to the oscillation stabilization
time set by OSTS. Note, therefore, that only the status up to the oscillation
stabilization time set by OSTS is set to OSTC after STOP mode is released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
When using the high-speed system clock oscillator and subsystem clock
oscillator, wire as follows in the area enclosed by the broken lines in the Figures
5-8 and 5-9 to avoid an adverse effect from wiring capacitance.
Note that the subsystem clock oscillator is designed as a low-amplitude circuit for
reducing power consumption.
When the internal oscillation clock is selected as the clock supplied to the CPU,
the prescaler generates various clocks by dividing the internal oscillator output (f
= 240 kHz (TYP.)).
The RSTOP setting is valid only when “Can be stopped by software” is set for
internal oscillator by the option byte.
To calculate the maximum time, set f
Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover
from the high-speed system clock to the subsystem clock (changing CSS from 0
to 1) should not beset simultaneously.
Simultaneous setting is possible, however, for selection of the CPU clock cycle
division factor (PCC0 to PCC2) and switchover from the subsystem clock to the
high-speed system clock (changing CSS from 1 to 0).
Setting the following values is prohibited when the CPU operates on the internal
oscillation clock.
Desired OSTC oscillation stabilization time
OSTS
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating
current flows.
Always make the ground point of the oscillator capacitor the same potential as
V
current flows.
Do not fetch signals from the oscillator.
CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 0
CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 1
CSS, PCC2, PCC1, PCC0 = 0, 1, 0, 0
SS
. Do not ground the capacitor to a ground pattern through which a high
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
Cautions
R
= 120 kHz.
Oscillation stabilization time set by
X
p. 118
p. 118
p. 118
p. 118
p. 120
p. 122
p. 129
p. 130
p. 131
p. 131
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