upd78f0134hgka1-9et-a Renesas Electronics Corporation., upd78f0134hgka1-9et-a Datasheet - Page 402

no-image

upd78f0134hgka1-9et-a

Manufacturer Part Number
upd78f0134hgka1-9et-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
operation. Even if CLME is set to 1 by software during the oscillation stabilization time (reset value of OSTS register
is 05H (2
the high-speed system clock ends. Monitoring is automatically started at the end of the oscillation stabilization time.
402
High-speed system clock
Internal oscillation clock
Internal oscillation clock
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
(CLME = 1 is set after RESET input and during high-speed system clock oscillation stabilization time)
Internal reset signal
Clock monitor status
16
CPU operation
/f
system clock
XP
High-speed
)) of the high-speed system clock, monitoring is not performed until the oscillation stabilization time of
(1) When internal reset is executed by oscillation stop of high-speed system clock
CLMRF
CLME
RESET
CLME
Monitoring
operation
Normal
(2) Clock monitor status after RESET input
Figure 21-3. Timing of Clock Monitor (1/4)
Oscillation
Oscillation
stopped
stopped
Reset
CHAPTER 21 CLOCK MONITOR
User’s Manual U16899EJ3V0UD
4 clocks of internal oscillation clock
Clock supply
17 clocks
Monitoring stopped
stopped
Oscillation stabilization time
Set to 1 by software
Normal operation (internal oscillation clock)
stabilization time
Waiting for end
of oscillation
Monitoring

Related parts for upd78f0134hgka1-9et-a