upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 496

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

496
Interrupt
Key
Interrupt
Function
Standby
Function
Function
MK1L: Interrupt
mask flag
register
PR1L: Priority
specification
flag register
EGP, EGN:
External
interrupt
rising/falling
edge enable
registers
Software
interrupt request
acknowledgement
Interrupt
request hold
KRM: Key
return mode
register
STOP mode,
HALT mode
STOP mode
Details of
Function
Be sure to set bits 6 and 7 of MK1L to 1.
Be sure to set bits 6 and 7 of PR1L to 1.
Select the port mode after clearing EGPn and EGNn to 0 because an edge may
be detected when the external interrupt function is switched to the port function.
Do not use the RETI instruction for restoring from the software interrupt.
The BRK instruction is not one of the above-listed interrupt request hold
instructions. However, the software interrupt activated by executing the BRK
instruction causes the IE flag to be cleared to 0. Therefore, even if a maskable
interrupt request is generated during execution of the BRK instruction, the
interrupt request is not acknowledged.
If any of the KRM0 to KRM3 bits used is set to 1, set bits 0 to 3 (PU70 to PU73) of
the corresponding pull-up resistor register 7 (PU7) to 1.
If KRM is changed, the interrupt request flag may be set. Therefore, disable
interrupts and then change the KRM register. After that, clear the interrupt
request flag and then enable interrupts.
The bits not used in the key interrupt mode can be used as normal ports.
The RSTOP setting is valid only when “Can be stopped by software” is set for
internal oscillator by the option byte.
STOP mode can be used only when CPU is operating on the high-speed system
clock or internal oscillation clock. HALT mode can be used when CPU is
operating on the high-speed system clock, internal oscillation clock, or subsystem
clock. However, when the STOP instruction is executed during internal oscillation
clock operation, the high-speed system clock oscillator stops, but internal
oscillator does not stop.
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction.
The following sequence is recommended for operating current reduction of the
A/D converter when the standby function is used: First clear bit 7 (ADCS) of the
A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and
then execute the HALT or STOP instruction.
If the internal oscillator is operating before the STOP mode is set, oscillation of the
internal oscillation clock cannot be stopped in the STOP mode. However, when
the internal oscillation clock is used as the CPU clock, the CPU operation is
stopped for 17/f
APPENDIX D LIST OF CAUTIONS
User’s Manual U16961EJ4V0UD
R
(s) after STOP mode is released.
Cautions
p. 322
p. 334
p. 323
p. 324
p. 328
p. 332
p. 334
p. 334
p. 335
p. 336
p. 336
p. 336
p. 336
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