upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 348

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

at 0000H and 0001H when the reset signal is input.
clock oscillation stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of
hardware is set to the status shown in Table 18-1. Each pin is high impedance during reset input or during the
oscillation stabilization time just after reset release, except for P130, which is low-level output.
oscillation clock after the CPU clock operation has stopped for 17/f
clock monitor sources is automatically released after the reset, and program execution starts using the internal
oscillation clock after the CPU clock operation has stopped for 17/f
and LVI circuit power supply detection is automatically released when V
program execution starts using the internal oscillation clock after the CPU clock operation has stopped for 17/f
(see CHAPTER 20 POWER-ON-CLEAR CIRCUIT and CHAPTER 21 LOW-VOLTAGE DETECTOR).
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The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by clock monitor high-speed system clock oscillation stop detection
(4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, high-speed system
When a high level is input to the RESET pin, the reset is released and program execution starts using the internal
Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin.
2. During reset input, the high-speed system clock and internal oscillation clock stop
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
oscillating.
input. However, the port pins become high-impedance, except for P130, which is set to low-
level output.
CHAPTER 18 RESET FUNCTION
User’s Manual U16961EJ4V0UD
R
(s). A reset generated by the watchdog timer and
R
(s) (see Figures 18-2 to 18-4). Reset by POC
DD
> V
POC
or V
DD
> V
LVI
after the reset, and
R
(s)