upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 343

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

Low-
voltage
detector
Option
byte
Flash
memory
Function
When used as
reset
Cautions for
low-voltage
detector
Oscillation
stabilization
time on power
application or
after reset
release
Control of
RESET pin
Selection of
system clock
source
Low-speed
internal
oscillates
PG-FP4 GUI
software setting
value example
Details of
Function
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the
microcontroller can be arbitrarily set by taking action (1) below.
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
If supply voltage (V
reset signal is not generated.
In a system where the supply voltage (V
vicinity of the LVI detection voltage (V
on how the low-voltage detector is used.
<1> When used as reset
<2> When used as interrupt
Interrupt requests may be frequently generated. Take (b) of action (2) below.
The setting of this option is valid only when the crystal/ceramic oscillation clock is
selected as the system clock source. No wait time elapses if the high-speed
internal oscillation clock or external clock input is selected as the system clock
source.
Because the option byte is referenced after reset release, if a low level is input to
the RESET pin before the option byte is referenced, then the reset state is not
released.
Also, when setting 0 to RMCE, connect the pull-up resistor.
Because the X1 and X2 pins are also used as the P23/ANI3 and P22/ANI2 pins,
the conditions under which the X1 and X2 pins can be used differ depending on
the selected system clock source.
(1) Crystal/ceramic oscillation clock is selected
The X1 and X2 pins cannot be used as I/O port pins because they are used as
clock input pins.
(2) External clock input is selected
Because the X1 pin is used as an external clock input pin, P121 cannot be used
as an I/O port pin.
(3) High-speed internal oscillation clock is selected
P23/ANI3 and P22/ANI2 can be used as I/O port pins.
If it is selected that low-speed internal oscillator cannot be stopped, the count
clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation clock.
If it is selected that low-speed internal oscillator can be stopped by software,
supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless
of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation mode
register (LSRCM). Similarly, clock supply is also stopped when a clock other than
the low-speed internal oscillation clock is selected as a count clock to WDT.
While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can
be supplied to the 8-bit timer H1 even in the STOP mode.
The above values are recommended values. Depending on the usage
environment these values may change, so set them after having performed
sufficient evaluations.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
DD
) ≥ detection voltage (V
Cautions
LVI
), the operation is as follows depending
DD
) fluctuates for a certain period in the
LVI
) when LVIM is set to 1, an internal
p. 201
p. 201
p. 205
p. 209
p. 209
p. 209
p. 210
p. 210
p. 217
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