upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 238

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
238
Note This setting is not required when the watchdog timer is not used.
Remark
<1> to <11> in Figure 16-22 correspond to <1> to <11> in 16.8.6 (previous page).
Figure 16-22. Example of Block Erase Operation in Self Programming Mode
<2> Set no. of block to be erased
<7> Clear & restart WDT counter
<8> Execute HALT instruction
<4> Set the same value as
that of FLAPH to FLAPHC
<11> Normal termination
<1> Set erase command
(VCERR and WEPRERR flags)
<5> Set FLAPLC to 00H
<3> Set FLAPL to 00H
<9> Check execution result
(WDTE = ACH)
(FLCMD = 03H)
Block erasure
<6> Clear PFS
to FLAPH
CHAPTER 16 FLASH MEMORY
Normal
User’s Manual U16994EJ3V0UD
Note
<10> Abnormal termination
Abnormal

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