upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 175

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1.
(Interruption priority INTP0 > INTP1 > INTTMH1 (refer to Table10-1))
INTP0 interrupt was first masked.
performed.
10.4.3 Interrupt request pending
execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated
during the execution. The following shows such instructions (interrupt request pending instruction).
In the interrupt INTTMH1 servicing, servicing is performed such that the INTP1 interrupt is given priority, since the
Afterwards, once the interrupt mask for INTP0 is released, INTP0 processing through multiple interrupts is
IE = 0: Interrupt request acknowledgment disabled
Some instructions may keep pending the acknowledgment of an instruction request until the completion of the
• Manipulation instruction for interrupt request flag register 0 (IF0)
• Manipulation instruction for interrupt mask flag register 0 (MK0)
INTTMH1
Main processing
Example 3. A priority is controlled by the Multiple interrupts
EI
Figure 10-9. Example of Multiple Interrupts (2/2)
IE = 0
CHAPTER 10 INTERRUPT FUNCTIONS
User’s Manual U16994EJ3V0UD
INTP0
INTP1
INTTNH1 servicing
PMK0 = 1
PMK0 = 0
RETI
EI
IE = 0
IE = 0
INTP1 servicing
INTP0 servicing
RETI
RETI
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