upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 334

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

334
Crystal/
ceramic
oscillator
16-bit
timer/
event
counters
00
Function
TM00: 16-bit
timer counter
00
CR000: 16-bit
timer capture/
compare
register 000
CR010: 16-bit
capture/
compare
register 010
Details of
Function
−
When using the crystal/ceramic oscillator, wire as follows in the area enclosed by
the broken lines in Figure 5-6 to avoid an adverse effect from wiring capacitance.
Even if TM00 is read, the value is not captured by CR010.
If TM00 is referred to during a timer count, a timer count will be stopped during
reference processing, and a timer count is resumed after reference processing is
finished.
Therefore, if processing which refers to TM00 is performed, an error will arise at a
timer count.
Set CR000 to other than 0000H in the clear & start mode entered on match
between TM00 and CR000. This means a 1-pulse count operation cannot be
performed when this register is used as an external event counter.
In the free-running mode and in the clear & start mode using the valid edge of the
TI000 pin, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated
when CR000 changes from 0000H to 0001H following overflow (FFFFH).
If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00),
TM00 continues counting, overflows, and then starts counting from 0 again. If the
new value of CR000 is less than the old value, therefore, the timer must be reset
to be restarted after the value of CR000 is changed.
The value of CR000 after 16-bit timer/event counter 00 has stopped is not
guaranteed.
The capture operation may not be performed for CR000 set in compare mode
even if a capture trigger is input.
When P21 is used as the input pin for the valid edge of TI010, it cannot be used
as a timer output (TO00). Moreover, when P31 is used as TO00, it cannot be
used as the input pin for the valid edge of TI010.
If the register read period and the input of the capture trigger conflict when CR000
is used as a capture register, the capture trigger input takes precedence and the
read data is undefined. Also, if the count stop of the timer and the input of the
capture trigger conflict, the capture trigger is undefined.
Changing the CR000 setting may cause a malfunction. To change the setting,
refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing
compare register during timer operation.
In the free-running mode and in the clear & start mode using the valid edge of the
TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated
when CR010 changes from 0000H to 0001H following overflow (FFFFH).
If the new value of CR010 is less than the value of 16-bit timer counter 0 (TM00),
TM00 continues counting, overflows, and then starts counting from 0 again. If the
new value of CR010 is less than the old value, therefore, the timer must be reset
to be restarted after the value of CR010 is changed.
The value of CR010 after 16-bit timer/event counter 00 has stopped is not
guaranteed.
The capture operation may not be performed for CR010 set in compare mode
even if a capture trigger is input.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring
• Always make the ground point of the oscillator capacitor the same potential
• Do not fetch signals from the oscillator.
near a signal line through which a high fluctuating current flows.
as V
current flows.
SS
APPENDIX C LIST OF CAUTIONS
. Do not ground the capacitor to a ground pattern through which a high
User’s Manual U16994EJ3V0UD
Cautions
p. 70
pp. 83,
115
pp. 83,
115
pp. 84,
115
p.84,
115
pp. 84,
115
pp. 84,
116
pp. 84,
118
pp. 84,
121
pp. 84,
117
p. 84
pp. 85,
115
pp. 85,
115
pp. 85,
116
pp. 85,
118
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