gt3200 SMC Corporation, gt3200 Datasheet - Page 25

• Manufacturer Part Number: gt3200
• Description: Usb2.0 Phy Ic
• Manufacturer: SMC Corporation

USB2.0 PHY IC
SMSC GT3200, SMSC USB3250
RXDATA[7:0]
7.3
TXDATA[7:0]
RXACTIVE
RXVALID
TXREADY
CLKOUT
TXVALID
CLK60
Figure 7.2 FS CLK Relationship to Transmit Data and Control Signals (8-bit mode)
Figure 7.3 FS CLK Relationship to Receive Data and Control Signals (8-bit mode)
bit then the byte boundary can be stretched to 45 CLK60 cycles, and two stuffed bits would result in
a 50 CLK60 cycles.
Figure 7.2
TXREADY is only asserted for one CLK60 per byte time to signal the SIE that the data on the TXDATA
lines has been read by the Macrocell. The SIE may hold the data on the TXDATA lines for the duration
of the byte time. Transitions of TXVALID must meet the defined setup and hold times relative to
CLK60.
Figure 7.3
RXACTIVE "frames" a packet, transitioning only at the beginning and end of a packet. However
transitions of RXVALID may take place any time 8 bits of data are available.
how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be
presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing
relationship is applied to the data and control signals.
This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer. The Elasticity
Buffer is used to compensate for differences between the transmitting and receiving clock domains.
The USB2.0 specification defines a maximum clock error of ±1000ppm of drift.
Clock and Data Recovery Circuit
DATA(n)
shows the relationship between CLK60 and the transmit data transfer signals in FS mode.
shows the relationship between CLK60 and the receive data control signals in FS mode.
PID
DATA1
DATA2
DATASHEET
DATA(n+1)
20
DATA3
Don't
Care
Figure 7.3
Revision 1.3 (10-05-04)
DATA(n+2)
DATA4
also shows