cy28416 Cypress Semiconductor Corporation., cy28416 Datasheet - Page 8

• Manufacturer Part Number: cy28416
• Description: Next Generation Ftg For Intel Architecture
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07657 Rev. *C
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal needs to be
synchronized internal to the device prior to powering down the
clock synthesizer. PD is also an asynchronous input for
powering up the system. When PD is asserted HIGH, all clocks
need to be driven to a LOW value and held prior to turning off
the VCOs and the crystal oscillator.
PD (Power-down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs must be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
high or tri-stated (depending on the state of the control register
drive mode bit) on the next diff clock# HIGH-to-LOW transition.
When the SMBus PD drive mode bit corresponding to the
differential (CPU, SRC, and DOT) clock output of interest is
programmed to ‘0’, the clock output must be held with “Diff
clock” pin driven high at 2 x Iref, and “Diff clock#” tri-state. If
the control register PD drive mode bit corresponding to the
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
PCI, 33 MHz
USB, 48MHz
DOT96C
DOT96T
REF
PD
Figure 3. Power-down Assertion Timing Waveform
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tri-state. Note the example in
Figure 3 shows CPUT = 133 MHz and PD drive mode = ‘1’ for
all differential outputs. This diagram and description is appli-
cable to valid CPU frequencies 100, 133, 166, 200, 266, 333,
and 400 MHz. In the event that PD mode is desired as the
initial power-on state, PD must be asserted high in less than
10 µs after asserting VTT_PWRGD#.
PD Deassertion
The power-up latency needs to be less than 1.8 ms. This is the
time from the deassertion of the PD pin or the ramping of the
power supply until the time that stable clocks are output from
the clock chip. All differential outputs stopped in a tri-state
condition resulting from power down must be driven high in
less than 300 µs of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are to be enabled within a few clock cycles
of each other. Figure 4 is an example showing the relationship
of clocks coming up. Unfortunately, we can not show all
possible combinations, designers need to insure that from the
first active clock output to the last takes no more than two full
PCI clock cycles.
CY28416
Page 8 of 15
[+] Feedback