cy28416 Cypress Semiconductor Corporation., cy28416 Datasheet - Page 2

• Manufacturer Part Number: cy28416
• Description: Next Generation Ftg For Intel Architecture
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07657 Rev. *C
Pin Definition
47,46,44,43
39,38
23,24
6
20
7
42
18
9,10,13,14
21
1
2
26,27,29,30,
34,35
31,32
17
19
45
11, 16
8
33, 37
40
22
48
12, 15
5
28, 36
41
25
4
3
Pin No.
CPUT/C[0:1]
CPUT2_ITP/SRCT4
CPUC2_ITP/SRCC4
DOT96T, DOT96C
FS_A/REF1
FS_B/48 MHz0
FS_C/REF0
IREF
ITP_EN/PCIF1
PCI
48 MHz1
SCLK
SDATA
SRCT/C[0:3]
SRCT2_SATA,
SRCC2_SATA
TEST_SEL/PCIF0
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
VTT_PWRGD#/PD
XIN
XOUT
Name
I/O, SE,
I
I/O, SE 3.3V tolerant input for CPU frequency/REF clock
I/O, SE 3.3V tolerant input for CPU frequency/48-MHz clock
I/O, SE Enable SRC4 or CPU2_ITP/PCIF clock.
O, DIF Differential CPU clock output.
O, DIF Selectable Differential CPU or SRC clock output.
O, DIF Differential 96-MHz clock output.
O, DIF Differential Serial reference clock.
O, DIF Differential Serial reference clock. Recommended output for SATA
/
O, SE 33-MHz clock output.
O, SE 48-MHz clock output. (Uses same control SMBus register as 48 MHz0 to
PWR 3.3V power supply for outputs
PWR 3.3V power supply for outputs
PWR 3.3V power supply for outputs
PWR 3.3V power supply for outputs
PWR 3.3V power supply for outputs
PWR 3.3V power supply for PLL
GND
GND
GND
GND
GND
GND
I, PD
Type
O, SE 3.3V tolerant input for CPU frequency/REF clock
PD
I/O
O
I
I
I
ITP_EN = 0 @VTT_PWRGD# assertion PIN 39,38 = SRCT4,SRCC4
ITP_EN = 1 @VTT_PWRGD# assertion PIN 39,38 = CPUT2_ITP,CPUC2_ITP
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
A precision resistor is attached to this pin, which is connected to the internal
current reference.
(sampled on the VTT_PWRGD# assertion). 0 = SRC4, 1 = CPU2_ITP
control enable/disable.)
SMBus compatible SCLOCK.
SMBus compatible SDATA.
LVTTL input for selecting HI-Z or Normal operation/33-MHz Clock
0 = Normal operation, 1 = HI-Z when VTT_PWRGD# is sampled
Ground for outputs
Ground for outputs
Ground for outputs
Ground for outputs
Ground for outputs
Ground for PLL
3.3V LVTTL Input. This pin is a level-sensitive strobe used to latch the FS_A,
FS_B, FS_C/TEST_SEL, and PCIF0/ITP_EN Inputs. After asserting
VTT_PWRGD# (active LOW), this pin becomes a realtime input for asserting
power-down (active HIGH)
14.318-MHz Crystal Input
14.318-MHz Crystal Output
Description
CY28416
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