cy28416 Cypress Semiconductor Corporation., cy28416 Datasheet - Page 3

• Manufacturer Part Number: cy28416
• Description: Next Generation Ftg For Intel Architecture
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07657 Rev. *C
Frequency Select Pins (FS_A, FS_B, and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B, and FS_C input values. For all logic
levels of FS_A, FS_B, and FS_C VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B, and FS_C transitions will be ignored, except in
test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 1. Frequency Select Table (FS_A FS_B)
T
Table 2. Command Code Definition
Table 3. Block Read and Block Write Protocol
FS_C
(6:0)
18:11
27:20
36:29
45:38
Bit
1
0
0
0
0
1
1
1
7
8:2
Bit
10
19
28
37
46
1
9
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
FS_B
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
0
0
1
1
0
0
1
1
Block Write Protocol
FS_A
1
1
1
0
0
0
0
1
2
C_EN bit set)
Description
100 MHz
133 MHz
166 MHz
200 MHz
266 MHz
CPU
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
SRC
Description
PCIF/PCI
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
27:21
37:30
18:11
Bit
8:2
10
19
20
28
29
38
1
9
RESERVED
Slave address – 7 bits
Acknowledge from slave
Acknowledge from slave
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Start
Write
Command Code – 8 Bits
Repeat start
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
REF0
Block Read Protocol
Description
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
DOT96
CY28416
Page 3 of 15
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
USB
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