cy28551-3 Cypress Semiconductor Corporation., cy28551-3 Datasheet - Page 8

• Manufacturer Part Number: cy28551-3
• Description: Universal Clock Generator For Intel, Via And Sis
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-05677 Rev. *D
Byte 5: Control Register 5
Byte 6: Control Register 6
Byte 7: Vendor ID
Bit
Bit
Bit
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
0
7
6
5
4
3
2
1
@Pup
@Pup
@Pup
HW
HW
HW
HW
HW
HW
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Revision Code Bit 3 Revision Code Bit 3
Revision Code Bit 2 Revision Code Bit 2
Revision Code Bit 1 Revision Code Bit 1
Revision Code Bit 0 Revision Code Bit 0
POWERGOOD
SATA_SS_OFF
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
PCIE_SS_OFF
FIX_LINK_PCI
CPU_SS_OFF
SW_RESET
PCIE_SS0
SEL24_48
CPU_SS1
CPU_SS0
Reserved
Reserved
Name
Name
Name
FSD
FSC
FSB
FSA
PLL2 (PCIEPLL) Spread Spectrum Selection
Software Reset.
When set, the device will assert a reset signal on SRESET# upon
completion of the block/word/byte write that set it. After asserting and
deasserting the SRESET# this bit will self clear (set to 0).
Reserved
LINK and PCI clock source selection
0 = PLL2(SRCPLL), 1 = PLL3 (SATAPLL)
FSD Reflects the value of the FSD pin sampled on power-up. 0 = FSD
was low during VTT_PWRGD# assertion.
FSC Reflects the value of the FSC pin sampled on power-up. 0 = FSC
was low during VTT_PWRGD# assertion.
FSB Reflects the value of the FSB pin sampled on power-up 0 = FSB was
LOW during VTT_PWRGD# assertion.
FSA Reflects the value of the FSA pin sampled on power-up. 0 = FSA was
LOW during VTT_PWRGD# assertion
Power Status bit:
0 = Internal power or Internal resets are NOT valid
1 = Internal power and Internal resets are valid
Read only Bit 7 sets to 0 when Bit 7 =0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
CPU (PLL1) Spread Spectrum Selection
00: –0.5% (peak to peak)
01: ±0.25% (peak to peak)
10: –1.0% (peak to peak)
11: ±0.5% (peak to peak)
PLL1 (CPUPLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on.
0: –0.5% (peak to peak)
0: –1.0% (peak to peak)
PLL2 (PCIEPLL) Spread Spectrum Enable
0: SRC spread off, 1: SRC spread on.
PLL3 (SATAPLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
24M/48-MHz output selection
0 = 48 MHz, 1 = 24 MHz
Reserved
Description
Description
Description
CY28551-3
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