cy28551-3 Cypress Semiconductor Corporation., cy28551-3 Datasheet - Page 6

• Manufacturer Part Number: cy28551-3
• Description: Universal Clock Generator For Intel, Via And Sis
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-05677 Rev. *D
Table 3. Byte Read and Byte Write Protocol (continued)
Control Registers
Byte 0: Control Register 0
Byte 1: Control Register 1
Byte 2: Control Register 2
Bit
Bit
Bit
5
4
3
2
1
0
7
6
7
6
5
4
3
2
1
0
7
6
Bit
@Pup
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Byte Write Protocol
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
SATA/PCIEX[T/C]0 SATA/PCIEX[T/C]0 Output Enable
SATA/DOT96]
PCIEX[T/C]6
PCIEX[T/C]5
PCIEX[T/C]4
PCIEX[T/C]3
PCIEX[T/C]2
CPU[T/C]1
CPU[T/C]0
Reserved
Reserved
Reserved
Reserved
24_48M
Name
Name
Name
REF2
REF1
REF0
48M
SATA/DOT96Output Enable
0 = Disable (Tri-state), 1 = Enable
24_48M Output Enable
0 = Disabled, 1 = Enabled
48M Output Enable
0 = Disabled, 1 = Enabled
REF2 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
Reserved
Reserved
Reserved
PCIEX[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
PCIEX[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
PCIEX[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
PCIEX[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
PCIEX[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
Reserved
0 = Disable (Tri-state), 1 = Enable
37:30
Bit
29
38
39
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Description
Description
Description
Byte Read Protocol
Description
CY28551-3
Page 6 of 29
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