cy28551-3 Cypress Semiconductor Corporation., cy28551-3 Datasheet
cy28551-3
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cy28551-3 Summary of contents
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... Champion Court • San Jose CY28551-3 ® ® PCI REF LINK DOT96 24_48M 48M Xout 41 VDDREF 40 SCLK 39 SDATA 38 VTTPWRG#/PD 37 CPUT0 36 CPUC0 CY28551-3 35 VDDCPU 34 CPUT1 33 CPUC1 32 VSSCPU 31 **DOC2 30 VSSA 29 VDDA , CA 95134-1709 • 408-943-2600 Revised August 03, 2006 [+] Feedback ...
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... Ground for outputs. ential serial reference clocks. The two multifunction pins are selected by MODE. Default PCIEX6. Intel type SR output buffer reference clocks. The two multifunction pins are selected by MODE. Default PCIEX6. Intel type SR output buffer Ground for outputs. CY28551-3 Page [+] Feedback ...
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... LVTTL input for Output enable of PCIEX 4,5 via register selection/33-MHz clock output. Internal 150k pull-down Intel Type-3A output buffer 3.3V-tolerant LVTTL input for Output enable of PCIEX 6,7 via register selection/33-MHz clock output. Internal 150K pull-down Intel Type-3A output buffer Ground for outputs. CY28551-3 Page [+] Feedback ...
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... CY28551-3 SRC PLL Gear CPU PCIE PCIE PCIE Constant N VCO M N 200 800 30 60 200 200 800 30 60 ...
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... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read CY28551-3 Page [+] Feedback ...
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... Disabled Enabled REF2 Output Enable 0 = Disabled Enabled REF1 Output Enable 0 = Disabled Enabled REF0 Output Enable 0 = Disabled Enabled CPU[T/C]1 Output Enable 0 = Disable (Tri-state Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state Enabled Reserved Reserved CY28551-3 Byte Read Protocol Description Description Description Description Page [+] Feedback ...
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... Allow control of CPU1 with assertion of CPU_STP Free Running 1 = Stopped with CPU_STP# Allow control of CPU0 with assertion of CPU_STP Free Running 1= Stopped with CPU_STP# Reserved Allow control of PCIEX with assertion of PCI_STP Free Running 1 = Stopped with PCI_STP# SW Frequency selection bits. See Figure 1. CY28551-3 Description Description Description Page [+] Feedback ...
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... FSA Reflects the value of the FSA pin sampled on power-up FSA was LOW during VTT_PWRGD# assertion Power Status bit Internal power or Internal resets are NOT valid 1 = Internal power and Internal resets are valid Read only Bit 7 sets to 0 when Bit 7 =0 Description Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 CY28551-3 Page [+] Feedback ...
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... Frequency. DOC[1:2] =01 RESERVED, Set = 0 RESERVED, Set = 0 Smooth switch Bypass 0: Activate SMSW block 1: Bypass and de-activate SMSW block. Smooth switch select 0: select CPU_PLL 1: select SRC_PLL. RESERVED, Set = 0 Description The DF1_N[8:0] will be used to configure CPU frequency for Dynamic Frequency. DOC[1:2] =01. CY28551-3 Page [+] Feedback ...
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... Watchdog timer time stamp selection 000: Reserved (test mode) 001 Time_Scale 010 Time_Scale 011 Time_Scale 100 Time_Scale 101 Time_Scale 110 Time_Scale 111 Time_Scale Watchdog timer enable, when the bit is asserted, Watchdog timer is triggered and time stamp of WD_Timer is loaded 0 = Disable Enable CY28551-3 Page [+] Feedback ...
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... FSEL[3:0] register will be used. Description The PCIE_DAF_N[8:0] will be used to configure PCIE frequency for Dial-A Frequency Description Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit CY28551-3 Page [+] Feedback ...
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... Crystal Recommendations The CY28551-3 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28551-3 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... Ce .................................................... External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) Multifunction Pin Selection In CY28551-3, some of the pins can provide different types of frequency, depending on the SEL[1:0] HW strapping pin setting, to support different chipset vendors. The configuration is shown as follows: LINK/DOT/SA SEL[1:0] ...
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... Watchdog Recovery Mode – This bit selects the location to recover from. One option is to recover from the HW settings (already stored in SMBUS registers for readback capability) and the second is to recover from a register called “Recovery N”. Default = 0 (Recover from the HW setting) CY28551-3 Page [+] Feedback ...
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... When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by 2-6 rising edges of the internal CPUC clock. The final state of the CY28551-3 Page [+] Feedback ...
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... The impact of asserting the PCI_STP# signal will be the following. The clock chip is to sample the PCI_STP# signal on a rising edge of PCIF clock. After detecting the PCI_STP# assertion low, all PCI and stoppable PCIF clocks will latch low CY28551-3 Page [+] Feedback ...
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... CLKREQ# drive mode bit is programmed to '1', the final state of all stopped DIF signals is low, both PCIEXT clock and PCIEXC clock outputs will not be driven. Figure 7. CPU_STP# De-Assertion > CY28551-3 Page [+] Feedback ...
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... PCI_STP# PCI_F PCI PCIEX 100MHz PE_REQ# PCIEXT(free running) PCIEXC(free running) PCIEXT(stoppable) PCIEXC(stoppable) Document #: 001-05677 Rev. *D Figure 8. PCI_STP# Assertion Figure 9. PCI_STP# De-Assertion Tdrive_PCIEX <15 ns Figure 10. CLKREQ# De-Assertion T < 10ns drive_PE_REQ# CY28551-3 Page [+] Feedback ...
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... VTT_PWRGD# = Low Delay > 0. Normal VDD_A = off Operation VTT_PWRGD# = toggle Figure 12. VTT_PWRGD# Timing Diagram Wait for Sample Sels Delay VTT_PWRGD# State 1 State 2 On CY28551-3 S2 Sample Inputs straps Wait for <1.8 ms Enable Outputs Device is not affected, VTT_PWRGD# is ignored State 3 On Page [+] Feedback ...
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... Condition 3.3 ± 5% SDATA, SCLK SDATA, SCLK Except internal pull-up resistors, 0 < Except internal pull-down resistors, 0 < – max. load and freq. per Figure 15 PD asserted, Outputs Tri-state CY28551-3 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 150 ° ...
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... Measured at crossing point clock Measured at crossing point clock Measured at crossing point clock Measured at crossing point clock Measured at crossing point clock Measured at crossing point clock CY28551-3 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps – 300 ppm ...
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... Measured at crossing point clock Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured differentially from ±150 mV Measured single-endedly from ±75 mV Math averages Figure 15 Math averages Figure 15 CY28551-3 Min. Max. Unit 4.91450 5.11063 ns 3.66463 3.85422 ns 2.91470 3.10038 ns 2 ...
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... Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point V OX Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point V OX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V CY28551-3 Min. Max. Unit 300 550 10.4156 10.4177 ns 10.1656 10.6677 ns – 250 ps – ...
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... Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V OX Measurement taken from cross point @1 µ Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V CY28551-3 Min. Max. Unit – 500 ps – 500 20.83125 20.83542 ns 20.48125 21.18542 ns 8.094 10 ...
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... Figure 13. Single-ended Load Configuration 22Ω 50Ω 12Ω 50Ω 12Ω 50Ω 12Ω 50Ω 12Ω 50Ω 12Ω 50Ω 12Ω 50Ω 12Ω 50Ω CY28551-3 Measurement Point 5 pF Measurement Point 5 pF Measurement Point 5 pF Measurement Point Measurement Point Measurement Point 5 pF Measurement Point ...
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... CY28551 ...
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... Figure 19. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Lead-free CY28551LFXC-3 56-pin QFN CY28551LFXC-3T 56-pin QFN – Tape and Reel Document #: 001-05677 Rev. *D Package Type CY28551-3 Product Flow Commercial, 0 ° ° C Commercial, 0 ° ° C Page [+] Feedback ...
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... MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. (PAD SIZE VARY BY DEVICE TYPE) 0.30[0.012] 0.50[0.020] 0°-12° 6.45[0.254] C 6.55[0.258] SEATING PLANE 2 C system, provided that the system conforms to the I CY28551-3 0.18[0.007] 0.28[0.011] PIN1 ID N 0.20[0.008 0.45[0.018] E-PAD 0.24[0.009] (4X) 0.60[0.024] 0.50[0.020] 51-85144-*D 2 ...
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... Document History Page Document Title: CY28551-3 Universal Clock Generator for Intel, VIA and SIS Document Number: 001-05677 REV. ECN NO. Issue Date ** 409135 See ECN *A 417501 See ECN *B 460525 See ECN *C 491623 See ECN *D 492449 See ECN Document #: 001-05677 Rev. *D Orig. of Description of Change ...