cy2sstu32866 SpectraLinear Inc, cy2sstu32866 Datasheet - Page 7
![no-image](/images/no-image-200.jpg)
cy2sstu32866
Manufacturer Part Number
cy2sstu32866
Description
1.8v, 25-bit 1 1 Or 14-bit 1 2 Jedec-compliant Data Register With Parity
Manufacturer
SpectraLinear Inc
Datasheet
1.CY2SSTU32866.pdf
(24 pages)
- Current page: 7 of 24
- Download datasheet (230Kb)
Rev 1.0, November 25, 2006
PAR_IN
D8-D13
D1−D6,
RESET
V REF
CLK
CLK
C1
C0
G2
H1
J1
A3, T3
G5
G1
G6
Figure 3. Parity logic Diagram for 1:2 register-B configuration (positive logic) C0=1, C1=1
11
Counter
R
2−Bit
(internal node)
CLK
D
R
LPS0
CLK
D
R
CE
CLK
Q
Q
Generator
Parity
11
0
1
D1−D6,
D8−D13
(internal node)
LPS1
D
R
CLK
CE
Q
D
R
CLK
D
R
D1−D6,
D8−D13
Q
CLK
11
Q
0
1
1
0
CY2SSTU32866
11
11
A2
Q1B−Q6B,
Q8B−Q13B
D2
Q1A−Q6A,
Q8A−Q13A
Page 7 of 24
PPO
QERR
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