cy2sstu32866 SpectraLinear Inc, cy2sstu32866 Datasheet - Page 3

• Manufacturer Part Number: cy2sstu32866
• Description: 1.8v, 25-bit 1 1 Or 14-bit 1 2 Jedec-compliant Data Register With Parity
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 25, 2006
Pin Definition
RESET#
CSR#
DCS#
D1
D2-3
D4
D5, 6, 8, 9,
10
D11
D12, 13
D14
D15-25
DODT
DCKE
Q1A
Q2A-3A
Q4A
Q5A, 6A, 8A,
9A, 10A
Q11A
Q12A, Q13A P5, R5
Q14A
Q1B
Q2B-3B
Q4B
Q5B, 6B, 8B,
9B, 10B,
Q11B
Pin Name
G2
J2
H2
B1, C1
E1, F1, K1, L1, M1
N1
P1, R1
T1
B2, C2, E2, F2, K2, L2,
M2, N2, P2, R2, T2
D1
A1
B5, C5
E5, F5, K5, L5, M5
N5
T5
(C0 = 0, C1 = 0)
(continued)
Pin Number
G2
J2
H2
B1, C1
E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data input – clocked in on the crossing points of
N1
P1, R1
T1
D1
A1
B5, C5
E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS#
N5
P5, R5
T5
E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS#
N6
B6, C6
(C0 = 0, C1 = 1)
Pin Number
G2
J2
H2
A1
B1, C1
D1
P1, R1
N1
T1
A5
B5, C5
D5
P5, R5
A6
B6, C6
D6
(C0 = 1, C1 = 1)
Pin Number
Asynchronous reset – resets registers and
disables Vref data and clock differential input
receivers
Chip Select – Disables D1-D24 when both CSR#
and DCS# are HIGH (V
Chip Select – Disables D1-D24 when both CSR#
and DCS# are HIGH (V
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
CY2SSTU32866
Description
DD
DD
)
)
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