cy2sstu32866 SpectraLinear Inc, cy2sstu32866 Datasheet - Page 5

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cy2sstu32866

Manufacturer Part Number
cy2sstu32866
Description
1.8v, 25-bit 1 1 Or 14-bit 1 2 Jedec-compliant Data Register With Parity
Manufacturer
SpectraLinear Inc
Datasheet
Rev 1.0, November 25, 2006
PAR_IN
D8-D25
D2−D3,
D5−D6,
RESET
V REF
CLK
CLK
C1
C0
G2
A3, T3
G5
G1
G6
H1
J1
Figure 1. Parity logic Diagram for 1:1 register configuration (positive logic) C0=0, C1=0
22
Counter
R
2−Bit
(internal node)
CLK
D
R
CLK
LPS0
D
R
CE
CLK
Q
Q
Generator
Parity
22
0
1
D2−D3,
D5−D6,
D8−D25
(internal node)
LPS1
D
R
CLK
CE
Q
D
R
CLK
D
R
CLK
Q
Q
D2−D3,
D5−D6,
D8−D25
22
0
1
1
0
CY2SSTU32866
22
A2
D2
Page 5 of 24
Q2−Q3,
Q5−Q6,
Q8−Q25
PPO
QERR

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