MM74HCT74M Fairchild Semiconductor, MM74HCT74M Datasheet - Page 5

IC FLIP FLOP DUAL D-TYPE 14-SOIC

MM74HCT74M

Manufacturer Part Number
MM74HCT74M
Description
IC FLIP FLOP DUAL D-TYPE 14-SOIC
Manufacturer
Fairchild Semiconductor
Series
74HCTr
Type
D-Typer
Datasheet

Specifications of MM74HCT74M

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
27MHz
Delay Time - Propagation
21ns
Trigger Type
Positive Edge
Current - Output High, Low
4.8mA, 4.8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Number Of Circuits
2
Logic Family
74HCT
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
35 ns
High Level Output Current
- 4.8 mA
Low Level Output Current
4.8 mA
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
4.5 V
Technology
CMOS
Number Of Bits
2
Number Of Elements
2
Clock-edge Trigger Type
Positive-Edge
Operating Supply Voltage (typ)
5V
Package Type
SOIC N
Frequency (max)
21MHz
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
14
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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©1984 Fairchild Semiconductor Corporation
MM74HCT74 Rev. 1.4.0
AC Electrical Characteristics
V
Note:
5. C
CC
t
t
t
Symbol
PHL
PHL
THL
current consumption, I
f
t
PD
C
REM
t
C
MAX
t
r
t
t
, t
, t
W
, t
, t
PD
5.0V ± 10%, C
S
H
IN
determines the no load dynamic power consumption, P
PLH
PLH
f
TLH
Maximum Operating Frequency
Maximum Propagation Delay from
Clock to Q or Q
Maximum Propagation Delay from
Preset or Clear to Q or Q
Minimum Removal Time Preset or
Clear to Clock
Minimum Setup Time Data to
Clock
Minimum Hold Time Clock to Data
Minimum Pulse Width Clock,
Preset or Clear
Maximum Clock Input Rise and
Fall Time
Maximum Output Rise and Fall
Time
Power Dissipation Capacitance
Maximum Input Capacitance
L
50 pF, t
S
Parameter
C
PD
r
V
CC
t
f
f + I
6ns unless otherwise specified.
CC
.
(5)
(per flip-flop)
Conditions
5
D
C
PD
Typ.
21
21
–3
10
9
5
T
V
A
CC
2
25°C
f + I
500
27
35
35
20
20
16
15
10
0
Guaranteed Limits
CC
V
CC
T
A
, and the no load dynamic
–40° to +85°C
500
21
44
44
25
25
20
19
10
0
www.fairchildsemi.com
Units
MHz
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns

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