LTC2431 Linear Technology, LTC2431 Datasheet - Page 25

• Manufacturer Part Number: LTC2431
• Description: (LTC2430 / LTC2431) 20-Bit No Latency Delta-Sigma ADCs
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/ C) are
used for the external source impedance seen by IN
IN
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA ( 10nA max), results
in a small offset shift. A 100 source resistance will create
a 0.1 V typical and 1 V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2430 or LTC2431 samples the
differential reference pins REF
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
may be required as reference filters in certain configura-
tions. Such capacitors will average the reference sam-
pling charge and the external source resistance will see a
quasi constant reference differential impedance. When
F
differential reference resistance is 15.6M
generate a gain error of approximately 0.032ppm for each
ohm of source resistance driving REF
= HIGH (internal oscillator and 50Hz notch), the typical
differential reference resistance is 18.7M
generate a gain error of approximately 0.027ppm for each
ohm of source resistance driving REF
is driven by an external oscillator with a frequency f
O
–
= LOW (internal oscillator and 60Hz notch), the typical
, the expected drift of the dynamic current, offset and
REF
< 0.01 F), the voltage on the sampling capacitor
REF
will deteriorate the converter offset and
U
U
+
and REF
W
+
+
–
or REF
or REF
transfering small
REF
–
–
which will
which will
U
> 0.01 F)
. When F
. When F
+
EOSC
and
O
O
(external conversion clock operation), the typical differ-
ential reference resistance is 2.4 • 10
ohm of source resistance drving REF
in 0.206 • 10
source resistance on the two reference pins is additive
with respect to this gain error. The typical FS errors for
various combinations of source resistance seen by the
REF
nected to these pins are shown in Figures 17 and 18.
Typical – FS errors are similar to + FS errors with opposite
polarity.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F
100 of source resistance driving REF
Figure 17a. +FS Error vs R
Figure 17b. – FS Error vs R
+
and REF
O
= LOW (internal oscillator and 60Hz notch), every
–20
–30
–40
–50
–10
–10
50
40
30
20
10
10
0
0
–6
1
1
–
V
V
V
V
V
F
T
V
V
V
V
V
F
T
O
O
A
CC
REF
REF
IN
IN
A
CC
REF
REF
IN
IN
pins and external capacitance C
• f
= GND
= 25 C
= GND
= 25 C
+
–
+
–
= 5V
= 5V
+
–
+
–
= 1.25V
= 3.75V
= 3.75V
= 1.25V
= 5V
= GND
10
= 5V
= GND
10
EOSC
C
LTC2430/LTC2431
C
REF
C
C
REF
C
REF
REF
REF
ppm gain error. The effect of the
C
= 0.001 F
= 0.01 F
REF
100
100
R
R
= 100pF
SOURCE
= 0.001 F
SOURCE
SOURCE
= 100pF
SOURCE
= 0.01 F
( )
( )
1k
1k
at REF
at REF
C
C
REF
REF
= 0pF
10k
10k
= 0pF
+
+
12
+
+
or REF
or REF
or REF
or REF
/f
2431 F17a
2431 F17b
EOSC
100k
100k
–
–
–
(Small C
(Small C
–
will result
translates
and each
REF
25
con-
24301f
IN
IN
)
)