LTC2431 Linear Technology, LTC2431 Datasheet - Page 19

• Manufacturer Part Number: LTC2431
• Description: (LTC2430 / LTC2431) 20-Bit No Latency Delta-Sigma ADCs
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to allow the device to
return to the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
(if EOC = 0) or t
during the falling edge of EOC). The value of t
if the device is using its internal oscillator (F
or HIGH). If F
frequency f
HIGH before time t
state. The conversion result is held in the internal static
shift register.
(INTERNAL)
SDO
SCK
SLEEP
CS
Hi-Z
EOSC
> t
OUTPUT
DATA
EOCtest
O
BIT 0
EOCtest
, then t
EOC
is driven by an external oscillator of
EOCtest
U
CONVERSION
Hi-Z
after EOC goes LOW (if CS is LOW
EOCtest
TEST EOC
EOCtest
SLEEP
, the device returns to the sleep
U
Hi-Z
is 3.6/f
(OPTIONAL)
after the falling edge of CS
TEST EOC
Figure 9. Internal Serial Clock, Reduced Data Output Length
W
ANALOG INPUT RANGE
SLEEP
EOSC
Hi-Z
–0.5V
<t
EOCtest
REF
. If CS is pulled
BIT 23
0.1V TO V
REFERENCE
EOC
EOCtest
TO 0.5V
O
VOLTAGE
= logic LOW
1 F
2.7V TO 5.5V
U
REF
CC
BIT 22
is 23 s
V
REF
REF
IN
IN
GND
CC
+
–
LTC2430/
LTC2431
+
–
BIT 21
SIG
SDO
SCK
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
CS
F
O
DATA OUTPUT
BIT 20
MSB
3-WIRE
SPI INTERFACE
V
BIT 19
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 18
LTC2430/LTC2431
BIT 8
V
CC
10k
EOCtest
CONVERSION
Hi-Z
TEST EOC
, the first rising
2431 F09
19
24301f