MM74HC74AM Fairchild Semiconductor, MM74HC74AM Datasheet

IC F/F W/CLR&SET DUAL D 14-SOIC

MM74HC74AM

Manufacturer Part Number
MM74HC74AM
Description
IC F/F W/CLR&SET DUAL D 14-SOIC
Manufacturer
Fairchild Semiconductor
Series
74HCr
Type
D-Typer
Datasheet

Specifications of MM74HC74AM

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
72MHz
Delay Time - Propagation
12ns
Trigger Type
Positive Edge
Current - Output High, Low
5.2mA, 5.2mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Number Of Circuits
2
Logic Family
74HC
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
110 ns
High Level Output Current
- 5.2 mA
Low Level Output Current
5.2 mA
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
2 V
Dc
837
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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©1983 Fairchild Semiconductor Corporation
MM74HC74A Rev. 1.3.0
MM74HC74A
Dual D-Type Flip-Flop with Preset and Clear
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
MM74HC74AM
MM74HC74ASJ
MM74HC74AMTC
MM74HC74AN
Order Number
Typical propagation delay: 20ns
Wide power supply range: 2V–6V
Low quiescent current: 40µA maximum (74HC Series)
Low input current: 1µA maximum
Fanout of 10 LS-TTL loads
All packages are lead free per JEDEC: J-STD-020B standard.
Package
Number
MTC14
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
General Description
The MM74HC74A utilizes advanced silicon-gate CMOS
technology to achieve operating speeds similar to the
equivalent LS-TTL part. It possesses the high noise
immunity and low power consumption of standard
CMOS integrated circuits, along with the ability to drive
10 LS-TTL loads.
This flip-flop has independent data, preset, clear, and
clock inputs and Q and Q outputs. The logic level
present at the data input is transferred to the output dur-
ing the positive-going transition of the clock pulse. Pre-
set and clear are independent of the clock and
accomplished by a low level at the appropriate input.
The 74HC logic family is functionally and pinout compat-
ible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by inter-
nal diode clamps to V
Package Description
CC
and ground.
February 2008
www.fairchildsemi.com

Related parts for MM74HC74AM

MM74HC74AM Summary of contents

Page 1

... Package Order Number Number MM74HC74AM M14A MM74HC74ASJ M14D MM74HC74AMTC MTC14 MM74HC74AN N14A Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1983 Fairchild Semiconductor Corporation MM74HC74A Rev. 1.3.0 ...

Page 2

... Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View Logic Diagram ©1983 Fairchild Semiconductor Corporation MM74HC74A Rev. 1.3.0 Truth Table Inputs PR CLR CLK Note: Q0 the level of Q before the indicated input conditions were established. 1. This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) level ...

Page 3

... V DC Input or Output Voltage IN OUT T Operating Temperature Range Input Rise or Fall Times 2. 4. 6.0V CC ©1983 Fairchild Semiconductor Corporation MM74HC74A Rev. 1.3.0 (2) Parameter Parameter 3 Rating –0.5 to +7.0V –1 +1.5V CC –0 +0.5V CC ±20mA ±25mA ±50mA –65°C to +150°C 600mW 500mW 260°C Min ...

Page 4

... For a power supply of 5V ±10% the worst case output voltages (V values should be used when designing with this supply. Worst case V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I IH the higher voltage and so the 6.0V values should be used. ©1983 Fairchild Semiconductor Corporation MM74HC74A Rev. 1.3.0 ( (V) Conditions Typ ...

Page 5

... Delay Preset or Clear Minimum Removal Time, REM Preset or Clear to Clock t Minimum Setup Time, Data to Clock s t Minimum Hold Time, Clock to Data H t Minimum Pulse Width Clock, Preset or Clear W ©1983 Fairchild Semiconductor Corporation MM74HC74A Rev. 1.3.0 t 6ns r f Parameter Conditions 5 Guaranteed Typ. Limit Units 72 ...

Page 6

... Maximum Input Rise r f and Fall Time C Power Dissipation PD (5) Capacitance C Maximum Input IN Capacitance Note determines the no load dynamic power consumption current consumption ©1983 Fairchild Semiconductor Corporation MM74HC74A Rev. 1.3 Conditions V (V) Typ. CC 2.0 22 4.5 72 6.0 94 2.0 34 4.5 12 6 ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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