AD9516-5 Analog Devices, Inc., AD9516-5 Datasheet - Page 32

• Manufacturer Part Number: AD9516-5
• Description: 14-output Clock Generator
• Manufacturer: Analog Devices, Inc.

AD9516-5
The current source lock detect provides a current of 110 μA when
DLD is true and shorts to ground when DLD is false. If a capacitor
is connected to the LD pin, it charges at a rate determined by the
current source during the DLD true time but is discharged nearly
instantly when DLD is false. By monitoring the voltage at the
LD pin (top of the capacitor), LD = high happens only after the
DLD is true for a sufficiently long time. Any momentary DLD
false resets the charging. By selecting a properly sized capacitor,
it is possible to delay a lock detect indication until the PLL is
stably locked and the lock detect does not chatter.
To use current source digital lock detect, do the following:
•
•
•
The LD pin comparator senses the voltage on the LD pin, and
the comparator output can be made available at the REFMON
pin control (0x01B[4:0]) or the STATUS pin control (0x017[7:2]).
The internal LD pin comparator trip point and hysteresis are given
in Table 13. The voltage on the capacitor can also be sensed by
an external comparator connected to the LD pin. In this case,
enabling the on-board LD pin comparator is not necessary.
External VCXO/VCO Clock Input (CLK/ CLK )
CLK is a differential input that can be used to drive the AD9516
clock distribution section. This input can receive up to 2.4 GHz.
The pins are internally self-biased, and the input signal should
be ac-coupled via capacitors.
Place a capacitor to ground on the LD pin
Set 0x01A[5:0] = 0x04
Enable the LD pin comparator (0x01D[3] = 1)
CLK
CLK
VS
COMPARATOR
AD9516-5
Figure 39. CLK Equivalent Input Circuit
Figure 38. Current Source Lock Detect
LD PIN
110µA
2.5kΩ
5kΩ
5kΩ
DLD
2.5kΩ
LD
REFMON
OR
STATUS
CLOCK INPUT
STAGE
C
V
OUT
Rev. 0 | Page 32 of 76
The CLK/ CLK input can be used either as a distribution only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the PLL. The CLK/ CLK input can be used
for frequencies up to 2.4 GHz.
Holdover
The AD9516 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a high impedance
state. This is useful when the PLL reference clock is lost. Holdover
mode allows the VCO to maintain a relatively constant frequency
even though there is no reference clock. Without this function,
the charge pump is placed into a constant pump-up or pump-
down state, resulting in a large VCO frequency shift. Because
the charge pump is placed in a high impedance state, any leakage
that occurs at the charge pump output or the VCO tuning node
causes a drift of the VCO frequency. This can be mitigated by
using a loop filter that contains a large capacitive component
because this drift is limited by the current leakage induced slew
rate (I
Both a manual holdover mode, using the SYNC pin, and an
automatic holdover mode are provided. To use either function,
the holdover function must be enabled (0x01D[0] and 0x01D[2]).
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves the
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state if there is no
reference clock present.
The B counter (in the N divider) is reset synchronously with the
charge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, the channel dividers should be set to ignore
the SYNC pin (at least after an initial SYNC event). If the dividers
are not set to ignore the SYNC pin, any time SYNC is taken low to
put the part into holdover, the distribution outputs turn off.
LEAK
/C) of the VCO control voltage.