AD9516-5 Analog Devices, Inc., AD9516-5 Datasheet - Page 12
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AD9516-5
Manufacturer Part Number
AD9516-5
Description
14-output Clock Generator
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9516-5.pdf
(76 pages)
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AD9516-5
Parameter
SDIO (WHEN INPUT)
SDIO, SDO (OUTPUTS)
TIMING
PD , SYNC , AND RESET PINS
Table 12.
Parameter
INPUT CHARACTERISTICS
RESET TIMING
SYNC TIMING
LD, STATUS, REFMON PINS
Table 13.
Parameter
OUTPUT CHARACTERISTICS
MAXIMUM TOGGLE RATE
ANALOG LOCK DETECT
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CS to SCLK Setup and Hold, t
CS Minimum Pulse Width High, t
Output Voltage High, V
Output Voltage Low, V
Capacitance
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
Pulse Width Low
Pulse Width Low
LOW
HIGH
DH
CLK
DS
OL
)
OH
Min
2.0
50
1.5
S
, t
DV
H
PWH
Typ
110
2
Max
0.8
1
Min
2.0
2.7
16
16
2
1.1
2
3
Unit
V
V
μA
μA
pF
ns
High speed clock cycles
Min
2.7
Typ
10
20
2
Typ
100
3
Rev. 0 | Page 12 of 76
Max
8
0.8
0.4
25
Max
0.4
Unit
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Unit
V
V
MHz
pF
Test Conditions/Comments
Each of these pins has an internal 30 kΩ pull-up resistor
High speed clock is CLK input signal
Test Conditions/Comments
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see Table 49, 0x017, 0x01A, and 0x01B
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs may
couple to output when any of these pins are toggling
On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
Test Conditions/Comments
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