AD9516-5 Analog Devices, Inc., AD9516-5 Datasheet - Page 24

• Manufacturer Part Number: AD9516-5
• Description: 14-output Clock Generator
• Manufacturer: Analog Devices, Inc.

AD9516-5
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9516 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 47 and Table 48 through Table 57). Each section or
function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
Mode1: Clock Distribution or External VCO < 1600 MHz
Mode 1 bypasses the VCO divider. It can only be used when the
external clock source is less than 1600 MHz due to the maximum
input frequency allowed at the channel dividers.
For clock distribution applications where the external clock is
<1600 MHz, the register settings shown in Table 18 should be used.
Table 18. Settings for Clock Distribution < 1600 MHz
Register
0x010[1:0] = 01b
0x1E1[0] = 1b
Description
PLL asynchronous power-down (PLL off )
Bypass the VCO divider as source for
distribution section
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When using the internal PLL with an external VCO <1600 MHz,
the PLL must be turned on.
Table 19. Settings for Using Internal PLL with External VCO
< 1600 MHz
Register
0x1E1[0] = 1b
0x010[1:0] = 00b
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the VCO/
VCXO. This loop filter determines the loop bandwidth and
stability of the PLL. Make sure to select the proper PFD polarity
for the VCO/VCXO being used.
Table 20. Setting the PFD Polarity
Register
0x010[7] = 0
0x010[7] = 1
Description
PFD polarity positive (higher control voltage
produces higher frequency)
PFD polarity negative (higher control
voltage produces lower frequency)
Description
Bypass the VCO divider as source for
distribution section
PLL normal operation (PLL on) along with other
appropriate PLL settings in 0x010 to 0x01E