IDT72T20128L6-7BB IDT, Integrated Device Technology Inc, IDT72T20128L6-7BB Datasheet - Page 6

• Manufacturer Part Number: IDT72T20128L6-7BB
• Description: IC FIFO 1KX20 2.5V 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20128L6-7BB

• Function: Synchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20128L6-7BB

PIN DESCRIPTION
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
D
(See Pin No.
table for details)
EF/OR
(M14)
ERCLK
(L16)
EREN
(K16)
FF/IR
(H3)
FSEL0
(J3)
FSEL1
(J2)
FWFT
(G2)
HSTL
(B7)
IW
(K1)
MARK
(E14)
MRS
(J1)
OE
(G15)
OW
(L3)
PAE
(L15)
PAF
(G3)
PRS
(K3)
Q
(See Pin No.
table for details)
RCLK
(G16)
Symbol &
0
0
(1)
Pin No.
-D
-Q
(1)
19
19
(1)
(1)
(1)
Data Inputs
Empty Flag/
Output Ready
Echo Read
Clock
Echo Read
Enable
Full Flag/
Input Ready
Flag Select Bit 0
Flag Select Bit 1
First Word Fall
Through
HSTL Select
Input Width
Mark Read
Pointer for
Retransmit
Master Reset
Output Enable
Output Width
Programmable
Almost-Empty
Flag
Programmable
Almost-Full Flag
Partial Reset
Data Outputs
Read Clock
Name
HSTL-LVTTL Data inputs for a 20-, or 10-bit bus. When using 10- bit mode, the unused input pins are in a don’t care
HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is
HSTL-LVTTL Read Clock Echo output, must be equal to or faster than the Qn data outputs.
HSTL-LVTTL Read Enable Echo output, used in conjunction with ERCLK.
HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is
HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output registers to all zeros. During Master
HSTL-LVTTL When HIGH, data outputs Q
HSTL-LVTTL PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n, which is
HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored
HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output registers to all zeros. During Partial
HSTL-LVTTL Data outputs for a 20-, or 10-bit bus. When in 10- bit mode, the unused output pins should not be connected.
HSTL-LVTTL Input clock when used in conjunction with REN for reading data from the FIFO memory and output
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
INPUT
INPUT
INPUT
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
LVTTL
LVTTL
INPUT
INPUT
INPUT
LVTTL
INPUT
INPUT
state. The data bus is sampled on both rising and falling edges of WCLK when WEN is enabled and DDR
Mode is enabled or on the rising edges of WCLK only in SDR Mode.
empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available
at the outputs.
empty. In FWFT mode, the IR function is selected. IR indicates whether or not there is space available
for writing to the FIFO memory.
During Master Reset, this input along with FSEL1 will select the default offset values for the programmable
flags PAE and PAF. There are four possible settings available.
During Master Reset, this input along with FSEL0 will select the default offset values for the programmable
flags PAE and PAF. There are four possible settings available.
During Master reset, selects First Word Fall Through or IDT Standard mode. FWFT is not available in
DDR mode. In SDR mode, the first word will always fall through on the rising edge.
input must be tied HIGH, otherwise it should be tied LOW.
During Master Reset, this pin, along with OW selects the bus width of the read and write port.
INPUT
operation will reset the read pointer to this position. There is an unlimited number to times to set the mark
location, but only the most recent location marked will be acknowledged.
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
programmable flag default settings, and single or double data clock mode.
No other outputs are affected by OE.
During Master Reset, this pin along with IW selects the bus width of the read and write port.
stored in the Empty Offset register. PAE goes LOW if the number of words in the FIFO memory is less than
offset n.
in the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than
or equal to m.
Reset, the existing mode (IDT standard or FWFT) and programmable flag settings are not affected.
The output data is clocked on both rising and falling edges of RCLK when REN is enabled and DDR Mode
is enabled or on the rising edges of RCLK only in SDR Mode.
register.
This input pin is used to select HSTL or 2.5V LVTTL device operation. If HSTL inputs are required, this
6
0
-Q
19
are in high impedance. When LOW, the data outputs Q
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
0
-Q
19
are enabled.