IDT72T20128L6-7BB IDT, Integrated Device Technology Inc, IDT72T20128L6-7BB Datasheet - Page 10

• Manufacturer Part Number: IDT72T20128L6-7BB
• Description: IC FIFO 1KX20 2.5V 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20128L6-7BB

• Function: Synchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20128L6-7BB

AC ELECTRICAL CHARACTERISTICS
(Commercial: V
NOTES:
1. All AC timings apply to both IDT Standard mode and First Word Fall Through mode.
2. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
Symbol
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
S1
S2
A
ASO
CLK1
CLK2
CLKH1
CLKH2
CLKL1
CLKL2
DS
DH
ENS
ENH
WCSS
WCSH
SCLK
SCKH
SCKL
SDS
SDH
SENS
SENH
RS
RSS
HRSS
RSR
RSF
OE
OHZ
REF
PAES
ERCLK
CLKEN
RCSLZ
RCSHZ
SKEW1
SKEW2
SKEW3
OLZ
WFF
PAFS
Clock Cycle Frequency SDR
Clock Cycle Frequency DDR
Data Access Time
Data Access Serial Output Time
Clock Cycle Time SDR
Clock Cycle Time DDR
Clock High Time SDR
Clock High Time DDR
Clock Low Time SDR
Clock Low Time DDR
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
WCS setup time
WCS hold time
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
Reset Pulse Width
Reset Setup Time
HSTL Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in High Z
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to Programmable Almost-Full Flag
Read Clock to Programmable Almost-Empty Flag
RCLK to Echo RCLK output
RCLK to Echo REN output
RCLK to Active from High-Z
RCLK to High-Z
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK & WCLK for EF/OR & FF/IR in DDR mode
Skew time between RCLK and WCLK for PAE and PAF
CC
= 2.5V ± 5%, T
(4)
(3)
Parameter
A
= 0°C to +70°C;Industrial: V
(4)
(4)
CC
= 2.5V ± 5%, T
(1)
IDT72T20108L4
IDT72T20118L4
IDT72T20128L4
IDT72T2098L4
Min.
Commercial
100
0.6
0.6
9.1
1.8
4.0
1.8
4.0
1.2
0.5
1.2
0.5
1.2
0.5
3.5
3.5
—
—
—
45
45
15
30
15
10
—
—
—
—
—
—
—
—
—
—
—
4
5
5
5
4
0
4
10
Max.
250
110
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.6
3.2
3.2
3.2
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
A
= -40°C to +85°C)
IDT72T20108L5
IDT72T20118L5
IDT72T20128L5
IDT72T2098L5
Min.
Commercial
100
0.6
0.6
2.3
4.5
2.3
4.5
1.5
0.5
1.5
0.5
1.5
0.5
—
—
10
—
45
45
15
30
15
10
—
—
—
—
—
—
—
—
—
—
—
5
5
5
5
4
0
4
4
5
Max.
200
100
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
4
IDT72T20108L6-7 IDT72T20108L10
IDT72T20118L6-7 IDT72T20118L10
IDT72T20128L6-7 IDT72T20128L10
IDT72T2098L6-7
Com’l & Ind’l
Min.
100
0.6
0.6
6.7
2.8
6.0
2.8
6.0
2.0
0.5
2.0
0.5
2.0
0.5
—
—
13
—
45
45
15
30
15
10
—
—
—
—
—
—
—
—
—
—
—
5
5
5
4
0
5
5
6
COMMERCIAL AND INDUSTRIAL
Max.
150
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
75
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
(2)
TEMPERATURE RANGES
IDT72T2098L10
FEBRUARY 13, 2009
Min.
Commercial
100
0.6
0.6
4.5
9.5
4.5
9.5
3.0
0.5
3.0
0.5
3.0
0.5
—
—
10
20
—
45
45
15
30
15
10
—
—
—
—
—
—
—
—
—
—
—
5
5
5
4
0
7
7
8
100
Max.
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
50
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
5
MHz
MHz
MHz
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns