CLA70000 Zarlink Semiconductor, CLA70000 Datasheet - Page 2

• Manufacturer Part Number: CLA70000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLA70000 Series
2
Core Cell Arrangement
•
•
forms the basic cell of the core array. This array element is
repeated in a regular fashion over the complete core area to
give an homogenous ‘Full Field’ (sea of gates) array. This
lends itself to hierarchical design, allowing pre-routed user
defined subcircuits to be repeated anywhere on the array. The
core cell structure together with all associated cell libraries
have been carefully designed to maximize the number of nets
which may be routed through the cell. This enables optimal
routing of both data flow and control signal distribution
schemes thus giving very high overall utilization factors. This
feature is of particular benefit in designs using highly
structured blocks such as memory or arithmetic functions.
I/O Buffer Arrangement
•
•
•
are therefore required to be robust and flexible. Both inputs
and outputs incorporate electrostatic discharge (ESD)
protection structures which can withstand in excess of 2KV,
and are highly resistant to latch-up due to the epitaxial
process. In addition the construction concepts used for the
I/O cells provide the designer with several hundred different
options of I/O cell configuration.
components for static protection, CMOS and TTL compatible
input stages, and a wide variety of intermediate and output
drive configurations. Included are Schmitt triggers, tristate
Supports compact macros
Allows high density routing
A four transistor group (2 NMOS and 2 PMOS) (fig.1)
Several hundred different I/O cell combinations
Programmable Slew rate Control on all Outputs
Excellent Latchup and ESD immunity
The I/O buffers are the interface to external circuitry and
The CLA70000 I/O buffers (fig.2) contain all the
INPUT
DATA
2.5 Volts
IBSK1, IBSK2 and IBSK3 have been characterised
to give the correct timing when connected to the OPT* cells.
D
slew rate
controlled
driver
SLEW RATE CONTROL
N
P
Fig 2. Slew Control & I/O Block
N
P
OPT3
controls, and slew rate controlled output buffers. All I/O buffer
locations can be configured as supply pads (VDD and VSS).
multiple high drive outputs need to be switched
simultaneously, as may occur on driving capacitive loads
such as buses. Using regular output buffers
inherently fast edge speed can lead to significant power
supply noise transients, with possible mis-operation as a
result. To overcome this problem. The CLA70000 family
includes a set of slew rate controlled output drivers, which use
proprietary design techniques to control the turn-on of the
output transistors (di/dt). These cells provide a significant
benefit in the trade off between switching current magnitude
and the number of supply pads required.
Slew rate control of output drivers is a useful feature when
2.5 Volts
VSS
Supply
VSS
Supply
VDD
Supply
VSS
Supply
Figure 1 - Diagrammatic representation of Array Core Cell
50 pF
PIN
IB1 IB2
OP1
I/O BLOCK
I/O BLOCK
Bonding
Pad
IB3 IB4 IB5
IP
OP2
Programmable
contacts
with their