CLA70000 Zarlink Semiconductor, CLA70000 Datasheet

CLA70000

Manufacturer Part Number

CLA70000

Description

High Density CMOS Gate Arrays

Manufacturer

Zarlink Semiconductor

Datasheet

1.CLA70000.pdf (17 pages)

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( DataSheet : www.DataSheet4U.com )

Recent advances in CMOS processing technology and

improvements in design architecture have led to the

development of a new generation of array-based ASIC

products with vastly improved gate integration densities. This

family of CLA70000

considerable advantages to the design of next generation

systems combining high performance and high complexity.

Features

•

Low power channelless arrays from 5,000 to 250,000

available gates (5 W / gate / MHz)

1 micron (0.8 micron effective) twin well epitaxial process

Typical gate delays of 400 ps (NAND2 , Fanout=2)

Comprehensive cell library including DSP, JTAG/BIST

and compiled memory cells (ROM blocks to 64K bits

and RAM blocks to 16K bits)

Extensive Range of Plastic and Ceramic Packages for

both Surface Mount and Through Board Assembly

Flexible I/O structure allows user to define power pad

locations

Fully supported on industry standard workstations and

in-house software

High drive output stages with slew rate control

Supports JTAG and BIST test philosophies (IEEE 1149-1

Test Procedures)

MIL 883C compliant product available (paragraph 1.2.1)

CLA70000

CLA71000

CLA72000

CLA73000

CLA74000

CLA75000

CLA76000

CLA77000

CLA78000

NUMBER

DEVICE

1 micron CMOS arrays brings

POWER PADS

I/O AND

100

120

160

200

256

304

DS2462

Overview

Semiconductors' sixth generation CMOS gate array product.

The family consists of nine arrays implemented on the latest

generation (1 micron) twin well epitaxial CMOS process. The

process in conjunction with the advanced layout and route

software, offers extremely high packing densities.

proven CLA60000 series with the emphasis being placed on

high speed, high packing density, and provision of

comprehensive cell libraries. The cell libraries encompass

new DSP and other specialized macros.

ASIC design software tools, as well as Zarlink

Semiconductor’s

Design support is provided by

design centers, each offering a variety of design routes, which

may be customized to individual customer requirements.

Product Details

figures given for usable gates. Actual gate utilization is

dependent on circuit structure, giving a range of 40 -70% for

two layer metallisation.

The CLA70000 gate array family is Zarlink

The array architecture is based upon the earlier well

Full design support is available for major industry standard

The CLA70000 array series is shown below with typical

COMPLEXITY

High Density CMOS Gate Arrays

GATE

110K

182K

256K

12K

19K

27K

39K

70K

proprietary PDS2 design environment.

CLA70000 Series

ISSUE 3.1

USABLE GATES

Zarlink Semiconductor’s

www.DataSheet4U.com

ESTIMATED

13.5K

17.5K

31.5K

49.5K

115K

2.5K

9.5K

82K

March 1992

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