CLA70000 Zarlink Semiconductor, CLA70000 Datasheet - Page 10

• Manufacturer Part Number: CLA70000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLA70000 Series
PDS2 - The Zarlink Semiconductor ASIC Design
System
design system. It provides a fully-integrated, technology
independent VLSI design environment for all Zarlink
Semiconductor CMOS SemiCustom products.
configuring according to the available machine resources. It
comprises design capture (schematic capture or VHDL),
testability analysis, logic simulation, fault simulation, auto
place and route, and back annotation. The system offers full
support for hierarchical design techniques, maintained from
design capture through to layout, as well as advanced design
management tools. PDS2 may be used either at a Zarlink
Semiconductor Design Center or under licence at the
customer’s premises. A three day training course is available
for first time users.
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design system, which offers a total design environment
including behavioral and functional level modelling.
Third Party Software Support
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party design tools including IKOS, Mentor, Verilog, and
Viewlogic at the time of printing. Please check with our Sales
Offices for the most recent additions. The design kits offer fully
detailed timing information for all cell libraries, netlist
extraction utilities, and post layout back annotation capability
where applicable. An example of a workstation design flow is
shown in fig 5 below. Please contact your local Zarlink
Semiconductor’s sales office for further information about
support of particular tools.
Test Vector
Generation
Behavioral, Functional, and Gate Level Modelling
VHDL and Third Party Links
Supports Hierarchical Design Techniques
EDIF 2.0 Interface
PDS2 is Zarlink Semiconductor’s own proprietary ASIC
PDS2 runs on Digital Equipment Computers and is self
Design Kits for major industry standard ASIC design
software tools
All libraries include fully detailed timing information
EDIF 2.0 Interface
Post layout back annotation available
Zarlink Semiconductor supports a wide range of third
Libraries
Schematic
Simulation
Symbols
Models
CLA
WORKSTATION
ENVIRONMENT
Figure 5 - Workstation Design Flow
Simulation
Schematic
Capture
Translation
Translation
Back -
Annotation
ERC &
Netlist
Vector
PDS
ENVIRONMENT
Test Program
Design
Verification
Generation
Place &
Route
MLE
Specifications
Thermal Management
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CMOS process geometry reduction, results in a
corresponding increase in power dissipation. SemiCustom
designers now have the ability to design circuits of 100,000
gates and over, and chip power consumption is (or should be)
a very important concern.
in power dissipation at this complexity. It is essential to offer
ultra low power core logic to maintain an acceptable overall
chip power budget.
CLA70000 arrays offer low power factors and a selection of
power packages. Dissipation of 5 W per gate per Mhz gate
power and 1 W per gate load, is lower than most competitive
arrays, with the reduced junction temperatures having the
added advantage
of improved performance and reliability.
CLA70000 POWER DISSIPATION CALCULATION
estimated by following the example (calculated for the CLA76XXX)
below.
Number of available gates
Assume percent gates used
Number of used gates (110102 X 0.4)
Assume 15% of gates switching during.
each clock cycle (44045 X 0.15)
Power dissipation/gate/Mhz
(gate fanout typically 2 loads)
Total core dissipation/Mhz (6607 X 0.007)
Number of available I/O pads
Percent of I/O pads used as Outputs
Number of I/O pads used as Outputs
Number of output buffers switching
each clock cycle (20%)
Dissipation/output buffers/Mhz/pF
Output loading
Power/output buffer/Mhz
Total output buffer dissipation/Mhz
Total Power dissipation/Mhz
Estimated dissipation of the circuit at the frequencies below is
Total Power at 10 Mhz clock rate
Total Power at 25Mhz clock rate
Lower power CMOS for better thermal management
Improved reliability
Power packages available
The increase in speed and density available through
The logic core of 100K plus gates is the dominant factor
To minimize this problem Zarlink Semiconductor’s
CLA70000 series power dissipation for any array can be
110112
40%
44045
6607
7 W
46.2 mW
200
40%
80
16
25 W
50 pF
1.25mW
20mW
66.2mW
0.66W
1.65W