CLA70000 Zarlink Semiconductor, CLA70000 Datasheet - Page 11

• Manufacturer Part Number: CLA70000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

AC Characteristics for Selected Cells
The CLA70000 technology library contains all the timing
information for each cell in the design library. This information
is accessible to the simulator, which calculates propagation
delays for all signal paths in the circuit design. The simulator
can automatically derate timings according to the various
factors such as:
Supply voltage variation (from nominal 5V)
Junction temperature
Processing tolerance - manufacturing spreads
Gate fanout - logic loading on gate outputs
Interconnection wiring - net loading on gate outputs
0.8
1.6
1.4
1.2
1
1.4
1.2
0.8
0.6
0.4
0.2
3
1
0
-60
Normalised Delay Multiplier Vs
Normalised Delay Multiplier Vs
3.5
-10
temperature
Temperature °C
Figure 6
FIgure 7
Voltage
4
Voltage
For initial assessments of feasibility, path delay multipliers
can be estimated by referring to the following graphs in
conjunction with the appropriate delays in the tables.
40
4.5
90
5
140
CLA70000 Series
5.5
11