MT18VDDT3272 Micron, MT18VDDT3272 Datasheet - Page 6

• Manufacturer Part Number: MT18VDDT3272
• Description: 184-Pin Registered DDR SDRAM DIMMs (x72)
• Manufacturer: Micron

GENERAL DESCRIPTION
high-speed CMOS, dynamic random-access, 256MB and
512MB memory modules organized in a x72 (ECC) con-
figuration. These modules use internally configured
quad-bank DDR SDRAM devices.
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch archi-
tecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM module effectively con-
sists of a single 2n-bit wide, one-clock-cycle data transfer
at the internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O pins.
ternally, along with data, for use in data capture at the
receiver. DQS is an intermittent strobe transmitted by
the DDR SDRAM during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
tial clock (CK0 and CK0#); the crossing of CK0 going
HIGH and CK0# going LOW will be referred to as the
positive edge of CK0. Commands (address and control
signals) are registered at every positive edge of CK0.
Input data is registered on both edges of DQS, and output
data is referenced to both edges of DQS, as well as to both
edges of CK0.
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used to
select the device bank and row to be accessed (BA0, BA1
select devices bank; A0-A11 select device row for the
256MB module, A0-A12 select device row for the 512MB
module). The address bits registered coincident with the
READ or WRITE command are used to select the device
bank and the starting device column location for the
burst access.
mable READ or WRITE burst lengths of 2, 4, or 8 locations.
An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of the
burst access.
multibank architecture of DDR SDRAM modules allows
for concurrent operation, thereby providing high effec-
tive bandwidth by hiding row precharge and activation
time.
32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
The MT18VDDT3272AG and MT18VDDT6472AG are
These DDR SDRAM modules use a double data rate
A bidirectional data strobe (DQS) is transmitted ex-
These DDR SDRAM modules operate from a differen-
Read and write accesses to the DDR SDRAM modules
These DDR SDRAM modules provide for program-
As with standard SDR SDRAM modules, the pipelined,
6
saving power-down mode. All inputs are compatible
with the JEDEC Standard for SSTL_2. All outputs are
SSTL_2, Class II compatible. For more information re-
garding DDR SDRAM operation, refer to the 128Mb and
256Mb DDR SDRAM data sheet.
SERIAL PRESENCE-DETECT OPERATION
ence-detect (SPD). The SPD function is implemented
using a 2,048-bit EEPROM. This nonvolatile storage de-
vice contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tween the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide eight unique DIMM/EEPROM
addresses.
REGISTER DEFINITION
MODE REGISTER
of operation of the DDR SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS latency
and an operating mode, as shown in the Mode Register
Diagram. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and BA1 =
0) and will retain the stored information until it is pro-
grammed again or the device loses power (except for bit
A8, which is self-clearing).
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded) when
all device banks are idle and no bursts are in progress, and
the controller must wait the specified time before initiat-
ing the subsequent operation. Violating either of these
requirements will result in unspecified operation.
specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A11 (for the 256MB
module) or A7-A12 (for the 512MB module) specify the
operating mode.
Burst Length
oriented, with the burst length being programmable, as
shown in Mode Register Diagram. The burst length de-
termines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for both
the sequential and the interleaved burst types.
An auto refresh mode is provided, along with a power-
These DDR SDRAM modules incorporate serial pres-
The mode register is used to define the specific mode
Reprogramming the mode register will not alter the
Mode register bits A0-A2 specify the burst length, A3
Read and write accesses to the DDR SDRAM are burst
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-pin DDR SDRAM DIMMs
256MB, 512MB (ECC x72)
©2002, Micron Technology, Inc.