MT18VDDT3272 Micron, MT18VDDT3272 Datasheet - Page 19

• Manufacturer Part Number: MT18VDDT3272
• Description: 184-Pin Registered DDR SDRAM DIMMs (x72)
• Manufacturer: Micron

NOTES (continued)
32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
34. The voltage levels used are derived from a
35. V
36. V
37. This maximum value is derived from the refer-
38. For slew rates of greater than 1V/ns the (LZ)
39. During initialzation, V
minimum V
practice, the voltage levels obtained from a
properly terminated bus will provide significantly
different voltage values.
width 3ns and the pulse width can not be greater
than 1/3 of the cycle rate. VIL undershoot:
VIL(MIN) = -1.5V for a pulse width
pulse width can not be greater than 1/3 of the cycle
rate.
enced test load. In practice, the values obtained in
a typical terminated design may reflect up to 310ps
less for
prevail over
tion.
t
transition will start about 310ps earlier.
equal to or less than V
may be 1.35V maximum during power up, even if
V
ohms of series resistance is used between the V
supply and the input pin.
RPRE(MAX) condition.
IH
DD
DD
/V
overshoot: V
and V
t
LZ(MIN) will prevail over
DDQ
t
HZ(MAX) and the last DVW.
DD
are 0 volts, provided a minimum of 42
t
Q must track each other.
DD
DQSCK(MAX) +
level and the refernced test load. In
IH
(MAX) = V
DD
DDQ
+ 0.3V. Alternatively, V
, V
TT
DD
t
RPST(MAX) condi-
, and V
Q+1.5V for a pulse
t
DQSCK(MIN) +
t
3ns and the
REF
HZ(MAX) will
must be
TT
TT
19
40. The current Micron part operates below the
41. Reserved for future use.
42. Reserved for future use.
43. Random addressing changing 50% of data
44. Random addressing changing 100% of data
45. CKE must be active (high) during the entire time a
46. IDD2N specifies the DQ, DQS and DM to be driven
47. Whenever the operating frequency is altered, not
48. Min
slowest JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
changing at every transfer.
changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
to a valid high or low logic level. IDD2Q is similar
to IDD2F except IDD2Q specifies the address and
control inputs to remain stable. Although IDD2F,
IDD2N, and IDD2Q are similar, IDD2F is “worst
case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
modules is .7ns, to facilitate proper system
operation.
REF later.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-pin DDR SDRAM DIMMs
t
CK value at CL=2.5 in the SPD for -26A
256MB, 512MB (ECC x72)
©2002, Micron Technology, Inc.