IDT72V285L10TF IDT, Integrated Device Technology Inc, IDT72V285L10TF Datasheet - Page 21

• Manufacturer Part Number: IDT72V285L10TF
• Description: IC FIFO SS 65536X18 10NS 64STQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V285L10TF

• Function: Asynchronous
• Memory Size: 1.1M (65K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V285L10TF

NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
NOTE:
1. OE = LOW
D
Q
WCLK
RCLK
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
WEN
0
0
REN
PAF
WCLK
In IDT Standard mode: D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
In FWFT mode: D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
RCLK and the rising edge of WCLK is less than t
SKEW2
RCLK
- D
- Q
WEN
REN
LD
15
15
LD
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENS
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
CLKL
t
ENH
SKEW2
DATA IN OUTPUT
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
REGISTER
CLKH
t
CLKH
1
TM
(2)
t
CLK
t
CLK
t
t
ENS
LDS
t
t
CLKL
DS
t
t
ENS
LDS
t
CLKL
OFFSET
PAE
2
21
t
PAF
t
t
t
ENH
DH
LDH
t
t
LDH
t
ENH
A
t
ENS
t
SKEW2
(3)
OFFSET
PAF
t
ENH
D - m words in FIFO
OFFSET
PAE
1
t
t
DH
t
ENH
LDH
t
t
LDH
ENH
t
A
COMMERCIAL AND INDUSTRIAL
(2)
PAF
). If the time between the rising edge of
TEMPERATURE RANGES
2
t
PAF
OFFSET
PAF
D-(m+1) words
in FIFO
4512 drw 19
4512 drw 17
4512 drw 18
(2)