LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 14

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 10:
Register 11:
Internal Memory ........................................................................................................................... 160
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Micro Direct Memory Access (μDMA) ........................................................................................ 189
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
14
Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 158
Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 159
ROM Control (RMCTL), offset 0x0F0 .............................................................................. 166
Flash Memory Address (FMA), offset 0x000 .................................................................... 167
Flash Memory Data (FMD), offset 0x004 ......................................................................... 168
Flash Memory Control (FMC), offset 0x008 ..................................................................... 169
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 171
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 172
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 173
USec Reload (USECRL), offset 0x140 ............................................................................ 174
ROM Version Register (RMVER), offset 0x0F4 ................................................................ 175
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 176
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 177
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 178
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 179
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 180
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 181
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 182
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 183
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 184
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 185
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 186
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 187
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 188
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 211
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 212
DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 213
DMA Status (DMASTAT), offset 0x000 ............................................................................ 217
DMA Configuration (DMACFG), offset 0x004 ................................................................... 219
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 220
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 221
DMA Channel Wait on Request Status (DMAWAITSTAT), offset 0x010 ............................. 222
DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 223
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 224
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 226
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 227
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 229
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 230
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 232
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 233
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 235
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 236
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 238
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 239
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 241
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 242
Preliminary
June 02, 2008