LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 100

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
System Control
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0011.33FF
100
Bit/Field
31:21
19:17
15:12
11:10
9:8
20
16
RO
RO
7
31
15
0
0
RO
RO
Register 16: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. The PWM, SARADC0,
MAXADCSPD, WDT, SWO, SWD, and JTAG bits mask the RCGC0, SCGC0, and DCGC0 registers.
Other bits are passed as 0. MAXADCSPD is clipped to the maximum value specified in DC1.
30
14
MINSYSDIV
0
0
MAXADCSPD
MINSYSDIV
RO
RO
29
13
reserved
reserved
reserved
0
1
Name
PWM
MPU
ADC
RO
RO
28
12
0
1
RO
RO
27
11
0
0
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
reserved
RO
RO
26
10
0
0
RO
MAXADCSPD
RO
Reset
25
0
9
1
0x3
0x3
0
1
0
1
0
1
Preliminary
RO
RO
24
0
8
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Module Present
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Module Present. When set, indicates that the ADC module is
present.
System Clock Divider. Minimum 4-bit divider value for system clock.
The reset value is hardware-dependent. See the RCC register for how
to change the system clock divisor using the SYSDIV bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Max ADC Speed. This field indicates the maximum rate at which the
ADC samples data.
MPU Present. When set, indicates that the Cortex-M3 Memory Protection
Unit (MPU) module is present. See the ARM Cortex-M3 Technical
Reference Manual for details on the MPU.
Value
0x3
Value
0x3
MPU
RO
RO
23
0
7
1
Description
Specifies a 50-MHz CPU clock with a PLL divider of 4.
Description
1M samples/second
HIB
RO
RO
22
0
6
1
TEMPSNS
RO
RO
21
0
5
1
PWM
PLL
RO
RO
20
1
4
1
WDT
RO
RO
19
0
3
1
reserved
SWO
RO
RO
18
0
2
1
SWD
RO
RO
17
0
1
1
June 02, 2008
JTAG
ADC
RO
RO
16
1
0
1